Joseph Rhodes

US Patent:

43542280, Oct 12, 1982

Filed:

Dec 20, 1979

Appl. No.:

6/105711

Inventors:

Victor S. Moore - Deerfield Beach FL
Wayne R. Kraft - Coral Springs FL
Joseph C. Rhodes - Boca Raton FL
William L. Stahl - Coral Springs FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 700

US Classification:

364200

Abstract:

A processor is provided that is fabricated on a single semiconductor substrate. The processor includes an AND array for receiving program instructions from input sources external of the processor and for generating product signals. An OR array is provided and interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array receives ones of the plurality of control signals and transfers data between the processor and data sources external of the processor. An arithmetic and logic unit array is also provided on the semiconductor substrate and interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals to generate output data. A control register is further provided and is interconnected to the OR array and the AND array for receiving ones of the plurality of control signals for controlling execution of the program instructions within the AND array.

US Patent:

46601716, Apr 21, 1987

Filed:

Dec 21, 1981

Appl. No.:

6/332585

Inventors:

Victor S. Moore - Pompano Beach FL
Wayne R. Kraft - Coral Springs FL
Joseph C. Rhodes - Boca Raton FL

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 1920
H03K 1300

US Classification:

364900

Abstract:

Apparatus and method for decoding computer operation codes. The operation code is decoded into a single product term in the AND array of a programmable logic array. That single product term is then processed through a clock driven sequencer to generate a plurality of sequential product terms. These sequential product terms are decoded by the OR array of the programmable logic array to generate a plurality of sequential time states comprising the decoded operation code.

US Patent:

46850805, Aug 4, 1987

Filed:

Feb 22, 1982

Appl. No.:

6/350663

Inventors:

Joseph C. Rhodes - Boca Raton FL
Victor S. Moore - Pompano Beach FL
Wayne R. Kraft - Coral Springs FL
John W. Barrs - Hialeah FL

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 900

US Classification:

364900

Abstract:

A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.

US Patent:

45946612, Jun 10, 1986

Filed:

Feb 22, 1982

Appl. No.:

6/350660

Inventors:

Victor S. Moore - Pompano Beach FL
Gerard A. Veneski - Boca Raton FL
Tony E. Parker - Boca Raton FL
Joseph C. Rhodes - Boca Raton FL
Wayne R. Kraft - Coral Springs FL
William L. Stahl - Coral Springs FL

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 928

US Classification:

364200

Abstract:

A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.

US Patent:

49319892, Jun 5, 1990

Filed:

Apr 15, 1987

Appl. No.:

7/038556

Inventors:

Joseph C. Rhodes - Boca Raton FL
Victor S. Moore - Pompano Beach FL
Wayne R. Kraft - Coral Springs FL
John W. Barrs - Hialeah FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 928

US Classification:

364900

Abstract:

A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.