Joseph Thomas Pawlowski

US Patent:

6438043, Aug 20, 2002

Filed:

Sep 2, 1998

Appl. No.:

09/145720

Inventors:

Dean Gans - Boise ID
Eric J. Stave - Boise ID
Joseph Thomas Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365194, 3652257

Abstract:

An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circuitry which can be programmed by the manufacturer prior to implementation by a user. The delay path adjustment feature is particularly applicable to adjusting output signal timing to allow the integrated circuit to be operated in an environment which requires slower communications speeds. The same integrated circuit, therefore, can also be implemented in an environment which allows for faster communications speeds.

US Patent:

6446169, Sep 3, 2002

Filed:

Aug 31, 1999

Appl. No.:

09/387031

Inventors:

Joseph T. Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1212

US Classification:

711131, 711149, 711150, 711146, 711167

Abstract:

The present invention includes a microprocessor having a system bus for exchanging data with a computer system, and a private bus for exchanging data with a cache memory system. Since the processor exchanges data with the cache memory system through the private bus, cache memory operations thus do not require use of the system bus, allowing other portions of the computer system to continue to function through the system bus. Additionally, the cache memory and the processor are able to exchange data in a burst mode while the processor determines from the tag data when a read or write miss is occurring.

US Patent:

6469954, Oct 22, 2002

Filed:

Aug 21, 2000

Appl. No.:

09/642355

Inventors:

John R. Wilford - Meridian ID
Joseph T. Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 800

US Classification:

365233, 36523002, 36523003, 36518902, 36518904, 36518905

Abstract:

An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAMs array reads out the full N bits simultaneously, the arrays address bus is freed up to latch in the next sequential address A so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the arrays address bus to begin latching in the next sequential address A so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

US Patent:

6493799, Dec 10, 2002

Filed:

Apr 24, 2001

Appl. No.:

09/841643

Inventors:

Joseph Thomas Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1316

US Classification:

711118, 710127

Abstract:

A logic which enables implementation of a 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by merging tag, and data into an order block of information to maximize bus utilization. The logic reduces the bus cycles from four cycles for an 80-bit to three cycles for a 96-bit implementation.

US Patent:

6570816, May 27, 2003

Filed:

Oct 21, 2002

Appl. No.:

10/274773

Inventors:

John R. Wilford - Meridian ID
Joseph T. Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 800

US Classification:

365233, 36523002, 36523003, 36518902, 36518904, 36518905

Abstract:

An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAMs array reads out the full N bits simultaneously, the arrays address bus is freed up to latch in the next sequential address A so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the arrays address bus to begin latching in the next sequential address A so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

US Patent:

6721233, Apr 13, 2004

Filed:

Feb 11, 2003

Appl. No.:

10/365233

Inventors:

John R. Wilford - Meridian ID
Joseph T. Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 800

US Classification:

365233, 36523002, 36523003, 36518902, 36518904, 36518905

Abstract:

An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAMs array reads out the full N bits simultaneously, the arrays address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the arrays address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

US Patent:

6725344, Apr 20, 2004

Filed:

Aug 6, 2002

Appl. No.:

10/213696

Inventors:

Joseph T. Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1200

US Classification:

711146, 711131, 711167, 711149, 711150

Abstract:

The present invention includes a microprocessor having a system bus for exchanging data with a computer system, and a private bus for exchanging data with a cache memory system. Since the processor exchanges data with the cache memory system through the private bus, cache memory operations thus do not require use of the system bus, allowing other portions of the computer system to continue to function through the system bus. Additionally, the cache memory and the processor are able to exchange data in a burst mode while the processor determines from the tag data when a read or write miss is occurring.

US Patent:

6757840, Jun 29, 2004

Filed:

Aug 21, 2000

Appl. No.:

09/642424

Inventors:

Joseph T. Pawlowski - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1208

US Classification:

714 7, 711104, 711118

Abstract:

In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not functioning properly. In addition, the burst length of the SRAM is increased to reduce the number of tag subarrays necessary for operation of the cache tag so any nonfunctional tag subarrays are no longer necessary. In accordance with the indications from the programmed laser fuses and the increased burst length, logic circuitry disables any nonfunctional tag subarrays, leaving only functional tag subarrays to provide tag functionality for the memory cache. As a result, an SRAM that is typically scrapped as a result of nonfunctional tag subarrays can, instead, be recovered for sale and subsequent use.