Jose M Salcedo

Author:

Jose Enrique Salcedo

ISBN #:

8460745791

Author:

Jose Enrique Salcedo

ISBN #:

8496083179

Author:

Jose Maria Salcedo

ISBN #:

8483893991

US Patent:

6340944, Jan 22, 2002

Filed:

Aug 21, 2000

Appl. No.:

09/643385

Inventors:

Ronald Chang - Fremont CA
Jose A. Salcedo - Livermore CA
Raphael Horton - Pleasanton CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H03M 144

US Classification:

341161, 341163

Abstract:

An analog-to-digital converter which has a low resolution and high resolution mode. In response to the low resolution mode signal, a switching circuit selects only certain of the digital bit outputs. In one embodiment, the analog-to-digital converter is a pipelined circuit with a number of stages. In response to the low resolution mode, a number of the stages are bypassed, so that only the needed stages for the smaller number of bits are used. The stages that are bypassed are preferably powered down, but not completely. By maintaining a small amount of bias current to the bypassed stages, they can quickly respond when a switch is made back to full resolution mode.

US Patent:

6774942, Aug 10, 2004

Filed:

Aug 17, 2000

Appl. No.:

09/642613

Inventors:

Jose A. Salcedo - Livermore CA
Srinivas N. Neti - San Jose CA
Charles A. Rogers - San Jose CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H04N 964

US Classification:

348243, 348257

Abstract:

An improved offset correction circuit for an image digitizing system having a correlated double sample and hold circuit, a programmable gain amplifier and an analog-to-digital converter. The output of the analog-to-digital converter is provided to a dual offset correction circuit. The dual offset correction circuit provides both first and second correction values as feedback signals. In one embodiment, the first correction value is a coarse correction which is applied prior to amplification by the programmable gain amplifier. The second correction value is a fine correction offset which is applied as feedback after the programmable gain amplifier.

US Patent:

55876846, Dec 24, 1996

Filed:

May 12, 1995

Appl. No.:

8/440272

Inventors:

Jose A. Salcedo - Livermore CA

Assignee:

Exar Corporation - San Jose CA

International Classification:

G05F 110
H03K 1722

US Classification:

327538

Abstract:

A method of including power control features to analog integrated circuits does not require the addition of separate power control input signal pin(s). One or more existing externally applied reference signals are sensed to determine if the signals are within specified operational limits. When the reference signals are outside of the operational limits the internal circuit blocks are switched off to their non-power dissipating state. When the reference signals are within the operational limits the internal circuit blocks are switched on to their normal operating state. This switching can be accomplished in various ways, including but not limited to a single switch in a series with the power supply or many distributed switches in each circuit block or stage.

US Patent:

20150222420, Aug 6, 2015

Filed:

Apr 14, 2015

Appl. No.:

14/686637

Inventors:

- Fremont CA, US
Jose Antonio SALCEDO - Livermore CA, US

International Classification:

H04L 7/04

Abstract:

The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

US Patent:

20140126678, May 8, 2014

Filed:

May 15, 2013

Appl. No.:

13/894719

Inventors:

- Fremont CA, US
JOSE ANTONIO SALCEDO - Livermore CA, US

Assignee:

EXAR CORPORATATION - Fremont CA

International Classification:

H04L 7/033

US Classification:

375375

Abstract:

The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.