Jose M Orro

US Patent:

20100250981, Sep 30, 2010

Filed:

Mar 30, 2009

Appl. No.:

12/414248

Inventors:

Marc R. Pamley - Durham NC, US
Jose M. Orro - Cary NC, US
Albert V. Makley - Morrisville NC, US

Assignee:

Lenova (Singapore) Pte. Ltd. - Singapore

International Classification:

G06F 1/32

US Classification:

713320, 713324

Abstract:

In the context of computer systems, the present invention broadly contemplates the ability to dynamically adjust the voltage and frequency of DRAM memory modules that are dual-voltage tolerant based on system performance. The invention allows a computer system to dynamically scale the memory voltage between a lower and a higher voltage, thereby allowing the system to save power when the system is idle or in low usage, but also allowing the system to realize the full memory performance when running more intensive applications.

US Patent:

20230099478, Mar 30, 2023

Filed:

Sep 29, 2021

Appl. No.:

17/489546

Inventors:

- Morrisville NC, US
Jose M Orro - Cary NC, US

International Classification:

G11C 11/406
G11C 11/4091
G11C 11/408
G11C 11/4099
G11C 11/4096
G11C 7/06

Abstract:

A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

US Patent:

20200310971, Oct 1, 2020

Filed:

Mar 31, 2019

Appl. No.:

16/371082

Inventors:

- Singapore, SG
JONATHAN R. HINKLE - RALEIGH NC, US
JOSE M. ORRO - CARY NC, US
THEODORE B. VOJNOVICH - RALEIGH NC, US

International Classification:

G06F 12/0804
G06F 1/28

Abstract:

Powering random access memory (RAM) modules with non-volatile memory components may include providing, by a power supply, a first output voltage to one or more RAM modules, each RAM module of the one or more RAM modules comprising a volatile memory component and a non-volatile memory component; providing, by the power supply, a second output voltage to one or more system components distinct from the one or more RAM modules; detecting a power event; sending, by the power supply, in response to detecting the power event, a signal to the one or more RAM modules to initiate a save operation, wherein the save operation comprises storing, for each of the one or more RAM modules, data from the volatile memory component to the non-volatile memory component; and ceasing, by the power supply, the second output voltage while maintaining the first output voltage to facilitate the save operation.