Jonathan J Muirhead

US Patent:

20140059511, Feb 27, 2014

Filed:

Aug 22, 2013

Appl. No.:

13/973998

Inventors:

Christopher Schuermyer - Happy Valley OR, US
Jonathan J. Muirhead - Tigard OR, US
Leo Chang - Taichung City, TW

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716136

Abstract:

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.

US Patent:

20120167028, Jun 28, 2012

Filed:

Nov 23, 2011

Appl. No.:

13/304094

Inventors:

John G. Ferguson - Tualatin OR, US
Jonathan J. Muirhead - Tigard OR, US
Bikram Garg - , US

International Classification:

G06F 17/50

US Classification:

716112

Abstract:

When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.

US Patent:

20210248301, Aug 12, 2021

Filed:

Apr 30, 2021

Appl. No.:

17/245834

Inventors:

- Plano TX, US
Jonathan James Muirhead - Portland OR, US

International Classification:

G06F 30/398
G03F 1/36
H01L 21/027

Abstract:

Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

US Patent:

20190266311, Aug 29, 2019

Filed:

Jan 24, 2019

Appl. No.:

16/256518

Inventors:

- Wilsonville OR, US
Sherif Hany Riad Mohammed Mousa - Beaverton OR, US
Jonathan James Muirhead - Portland OR, US

International Classification:

G06F 17/50
G03F 1/36
G03F 1/00

Abstract:

Aspects of the disclosed technology relate to techniques of pattern-based resolution enhancement. Surrounding areas for a plurality of geometric layout elements in a layout design are partitioned into geometric space elements. The plurality of geometric layout elements and the geometric space elements are grouped, through pattern classification, into geometric layout element groups and geometric space element groups, respectively. Optical proximity correction is performed for each of the geometric layout element groups and sub-resolution assist feature insertion is performed for each of the geometric space element groups. The results are applied to the plurality of geometric layout elements and the geometric space elements in the layout design.

US Patent:

20180307791, Oct 25, 2018

Filed:

Jan 17, 2018

Appl. No.:

15/873833

Inventors:

- Wilsonville OR, US
Jonathan James Muirhead - Portland OR, US
Alex Joseph Pearson - Wilsonville OR, US
William Matthew Hogan - Wilsonville OR, US

International Classification:

G06F 17/50
G06K 9/62

Abstract:

Aspects of the disclosed technology relate to techniques of context-aware pattern matching and processing. A circuit design is analyzed to identity circuit components of interest. Reference layout patterns that are associated with the circuit components of interest are extracted from a layout design based on the association of circuit components of the circuit design with geometric elements of the layout design. Pattern matching is performed to identify layout patterns that match the reference layout patterns. The identified layout patterns are then processed.

US Patent:

20170337300, Nov 23, 2017

Filed:

Jan 31, 2017

Appl. No.:

15/421421

Inventors:

- Wilsonville OR, US
Sridhar Srinivasan - Tualatin OR, US
Jonathan J. Muirhead - Tualatin OR, US

International Classification:

G06F 17/50

Abstract:

A user or other source may specify one or more components in logical design data, such as schematic netlist design data. Based upon the provided logical component, portions of the physical design data that correspond to the logical component are selected. The selected physical design data corresponding to the specified logical component is then compared with a defined geometric element pattern, to determine if the corresponding physical design data matches the defined pattern. The results of the match analysis can be reported to a user as visual images, new design data, or both. Alternately or additionally, the selected physical design data may be modified based upon the results of the match analysis.

US Patent:

20170103158, Apr 13, 2017

Filed:

Sep 12, 2016

Appl. No.:

15/263014

Inventors:

- Wilsonville OR, US
Christopher Schuermyer - Happy Valley OR, US
Jonathan J. Muirhead - Tigard OR, US
Chen-Yi Chang - Taichung City, TW

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

Abstract:

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.

US Patent:

20150067621, Mar 5, 2015

Filed:

Sep 5, 2013

Appl. No.:

14/019529

Inventors:

- Wilsonville OR, US
Sridhar Srinivasan - Tualatin OR, US
Jonathan J. Muirhead - Tualatin OR, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716106

Abstract:

A user or other source may specify one or more components in logical design data, such as schematic netlist design data. Based upon the provided logical component, portions of the physical design data that correspond to the logical component are selected. The selected physical design data corresponding to the specified logical component is then compared with a defined geometric element pattern, to determine if the corresponding physical design data matches the defined pattern. The results of the match analysis can be reported to a user as visual images, new design data, or both. Alternately or additionally, the selected physical design data may be modified based upon the results of the match analysis.