Jonathan R Belk

US Patent:

7106758, Sep 12, 2006

Filed:

Aug 3, 2001

Appl. No.:

09/921945

Inventors:

Jonathan R. Belk - Richardson TX, US
Richard A. Nichols - Richardson TX, US

Assignee:

ADC Telecommunications, Inc. - Eden Prairie MN

International Classification:

H04J 3/06
H04L 12/28
H04L 12/56
H04J 1/16
H04J 3/14

US Classification:

370503, 37039562, 370516, 370518, 375354

Abstract:

A method for synchronizing a service clock at a destination node with a service clock at a source node is provided. The method includes receiving data packets from a source node at at least one port of the destination node. At the destination node, the method determines control values for a numerically controlled oscillator for a plurality of time periods. The method selectively uses the control values to set the frequency of a service clock at the destination node for use in receiving data packets.

US Patent:

20070019686, Jan 25, 2007

Filed:

Sep 11, 2006

Appl. No.:

11/530618

Inventors:

Jonathan Belk - Richardson TX, US
Richard Nichols - Richardson TX, US

Assignee:

ADC Telecommunications, Inc. - Eden Prairie MN

International Classification:

H04J 3/06

US Classification:

370516000

Abstract:

A method for controlling a local clock in a node coupled to a packet network is disclosed. The method involves generating a first control signal based on RTS values received during a first period of time and generating at least one additional control signal based on RTS values received during at least one additional period of time. The method further involves selecting one of the first and at least one additional control signals to control the frequency of a local clock.

US Patent:

6721328, Apr 13, 2004

Filed:

Nov 19, 1999

Appl. No.:

09/443662

Inventors:

Richard A. Nichols - Richardson TX
Jonathan R. Belk - Richardson TX

Assignee:

ADC Telecommunications, Inc. - Eden Prairie MN

International Classification:

H04L 1228

US Classification:

37039562, 370518, 370503, 370474

Abstract:

The present invention includes a method for clock recovery in a packet network. The method includes a network which receives data packets at a destination node. Then the data packets are stored in a buffer. The data packets are read out of the buffer by using a locally generated clock. The fill level of the buffer is monitored over a first period of time. A relative maximum fill level for the buffer is identified during the first period of time. Further, the relative maximum fill level is used to control the frequency of the locally generated clock so as to control the rate at which data is read out of the buffer.

US Patent:

20210209460, Jul 8, 2021

Filed:

Jan 3, 2020

Appl. No.:

16/734092

Inventors:

- Redmond WA, US
Mattheus C. HEDDES - Woodinville WA, US
Deepak GOEL - San Jose CA, US
Jonathan R. BELK - McKinney TX, US

International Classification:

G06N 3/08
G06N 20/00
G06F 9/38
H04L 29/08

Abstract:

Embodiments of the present disclosure include techniques for processing neural networks. Various forms of parallelism may be implemented using topology that combines sequences of processors. In one embodiment, the present disclosure includes a computer system comprising a plurality of processor groups, the processor groups each comprising a plurality of processors. A plurality of network switches are coupled to subsets of the plurality of processor groups. A subset of the processors in the processor groups may be configurable to form sequences, and the network switches are configurable to form at least one sequence across one or more of the plurality of processor groups to perform neural network computations. Various alternative configurations for creating Hamiltonian cycles are disclosed to support data parallelism, pipeline parallelism, layer parallelism, or combinations thereof.

US Patent:

20210211787, Jul 8, 2021

Filed:

May 26, 2020

Appl. No.:

16/883814

Inventors:

- Redmond WA, US
Mattheus C. HEDDES - Woodinville WA, US
Jonathan R. BELK - McKinney TX, US

International Classification:

H04Q 11/00
G06N 3/02

Abstract:

Embodiments of the present disclosure include techniques for processing neural networks. Various forms of parallelism may be implemented using topology that combines sequences of processors. In one embodiment, the present disclosure includes a computer system comprising one or more processor groups, the processor groups each comprising a plurality of processors. A plurality of network switches are coupled to subsets of the plurality of processor groups. In one embodiment, the switches may be optical network switches. Processors in the processor groups may be configurable to form sequences, and the network switches are configurable to form at least one sequence across one or more of the plurality of processor groups to perform neural network computations. Various alternative configurations for creating Hamiltonian cycles are disclosed to support data parallelism, pipeline parallelism, layer parallelism, or combinations thereof.