Jon S Berry

Author:

Jon Berry

ISBN #:

0070251118

US Patent:

20040021154, Feb 5, 2004

Filed:

Jul 31, 2002

Appl. No.:

10/210132

Inventors:

Michael Maldei - Durham NC, US
Jinhwan Lee - Cary NC, US
Guenter Gerstmeier - Chapel Hill NC, US
Brian Cousineau - Burlington NC, US
Jon Berry - Raleigh NC, US
Steven Baker - Apex NC, US
Malati Hedge - Cary NC, US

Assignee:

Infineon Technologies North America Corp.

International Classification:

H01L027/148

US Classification:

257/218000

Abstract:

A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

US Patent:

20040094810, May 20, 2004

Filed:

Nov 14, 2002

Appl. No.:

10/294329

Inventors:

Michael Maldei - Durham NC, US
Brian Cousineau - Burlington NC, US
Guenter Gerstmeier - Chapel Hill NC, US
Jon Berry - Durham NC, US
Steven Baker - Morrisville NC, US
Jinhwan Lee - Raleigh NC, US

Assignee:

Infineon Technologies North America Corp.

International Classification:

H01L029/76

US Classification:

257/411000

Abstract:

A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

US Patent:

20040173868, Sep 9, 2004

Filed:

Mar 6, 2003

Appl. No.:

10/383191

Inventors:

Michael Maldei - Durham NC, US
Malati Hegde - Cary NC, US
Guenter Gerstmeier - Chapel Hill NC, US
Jinwhan Lee - Raleigh NC, US
Steven Baker - Morrisville NC, US
Jon Berry - Raleigh NC, US
Brian Cousineau - Burlington NC, US
Wenchao Zheng - Raleigh NC, US

International Classification:

H01L029/00

US Classification:

257/503000

Abstract:

A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

US Patent:

20050062111, Mar 24, 2005

Filed:

Oct 7, 2004

Appl. No.:

10/960735

Inventors:

Michael Maldei - Durham NC, US
Jinhwan Lee - Cary NC, US
Guenter Gerstmeier - Chapel Hill NC, US
Brian Cousineau - Burlington NC, US
Jon Berry - Raleigh NC, US
Steven Baker - Apex NC, US
Malati Hedge - Cary NC, US

International Classification:

H01L029/76

US Classification:

257401000

Abstract:

A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

US Patent:

20050130352, Jun 16, 2005

Filed:

Dec 3, 2004

Appl. No.:

11/003592

Inventors:

Michael Maldei - Durham NC, US
Brian Cousineau - Burlington NC, US
Guenter Gerstmeier - Chapel Hill NC, US
Jon Berry - Durham NC, US
Steven Baker - Morrisville NC, US
Jinhwan Lee - Raleigh NC, US

International Classification:

H01L021/82
H01L021/336
H01L021/8234
H01L027/10
H01L029/739

US Classification:

438128000, 257202000

Abstract:

A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

US Patent:

20060244483, Nov 2, 2006

Filed:

May 2, 2005

Appl. No.:

11/118374

Inventors:

Jon Berry - Raleigh NC, US

International Classification:

H03K 19/173

US Classification:

326038000

Abstract:

A system and method for distributing signals throughout an integrated circuit (IC). The system comprises a transmitter unit and a plurality of receiver units. The transmitter unit combines a plurality of signals into a serial signal stream and couples the serial signal stream to a conductor for distribution to a plurality of destinations in the IC. There is a receiver unit at each of the plurality of destinations and connected to the conductor. Each receiver unit extracts one of the plurality of signals from the serial signal stream received on the conductor. The transmitter unit comprises a multiplexer circuit and a counter circuit and time multiplexes the plurality of signals to form a serial signal stream, wherein a signal is selected for a time slot based on a count value of the counter circuit. The counter signal is also supplied to each receiver unit, which uses the counter signal to determine when to latch a signal from the serial signal stream.