John Anthony Walters

US Patent:

20090309576, Dec 17, 2009

Filed:

Jun 13, 2008

Appl. No.:

12/138573

Inventors:

John Ryan Kess - Bloomington MN, US
John Charles Walters - McPherson KS, US

International Classification:

G01P 3/44
B23P 11/00

US Classification:

324174, 2988806

Abstract:

A speed pick-up ring includes a main body having a plurality of targets and defining a plurality of notches. Each notch is disposed between adjacent targets. Each notch includes a base wall, a first sidewall and an oppositely disposed second sidewall. The base wall includes a convex portion. A fluid device includes a housing and a variable reluctance speed sensor engaged to the housing. The fluid device further includes a speed pick-up ring disposed within the housing. The speed pick-up ring includes a main body having a plurality of targets and defining a plurality of notches. Each notch is disposed between adjacent targets. Each notch includes a base wall, a first sidewall that is generally concave and an oppositely disposed second sidewall that is generally concave. The base wall includes a convex portion.

US Patent:

54787718, Dec 26, 1995

Filed:

Dec 19, 1994

Appl. No.:

8/359006

Inventors:

Tsiu C. Chan - Carrollton TX
Frank R. Bryant - Denton TX
John L. Walters - Carrollton TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H01L 2170

US Classification:

437 57

Abstract:

An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

US Patent:

50652257, Nov 12, 1991

Filed:

Jul 31, 1990

Appl. No.:

7/560384

Inventors:

Frank R. Bryant - Denton TX
John L. Walters - Carrollton TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H01L 2348
H01L 4902
H01L 2702
H01L 2904

US Classification:

357 71

Abstract:

A semiconductor device is described in which a conductive layer overlaps a dielectric layer forming a composite electrical device deposited over selected portions of a semiconductor substrate chemically isolating the conductive layer portion of the composite electrical device from the substrate, thereby preventing difffusion of dopant material through the dielectric layer into and out of the conductive layer while simultaneously allowing for tunneling of electrons through the dielectric layer to and from the conductive layer and the semiconductor substrate.

US Patent:

58411950, Nov 24, 1998

Filed:

May 24, 1995

Appl. No.:

8/448703

Inventors:

Lun-Tseng Lu - Grand Praire TX
Fu-Tai Liou - Carrollton TX
Che-Chia Wei - Plano TX
John Leonard Walters - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 23532

US Classification:

257774

Abstract:

A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

US Patent:

52468836, Sep 21, 1993

Filed:

Feb 6, 1992

Appl. No.:

7/832088

Inventors:

Lun-Tseng Lu - Grand Prairie TX
Fu-Tai Liou - Carrollton TX
Che-Chia Wei - Plano TX
John L. Walters - Carrollton TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H01L 21302

US Classification:

437195

Abstract:

A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

US Patent:

56704240, Sep 23, 1997

Filed:

Oct 13, 1995

Appl. No.:

8/542815

Inventors:

Tsiu Chiu Chan - Carrollton TX
Frank Randolph Bryant - Denton TX
John Leonard Walters - Carrollton TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H01L 2144

US Classification:

437193

Abstract:

An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

US Patent:

54897971, Feb 6, 1996

Filed:

Apr 11, 1995

Appl. No.:

8/420353

Inventors:

Tsiu C. Chan - Carollton TX
Frank R. Bryant - Denton TX
John L. Walters - Carrollton TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H01L 2976
H01L 2994
H01L 2711

US Classification:

257382

Abstract:

An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.