John R Vollaro

US Patent:

48336386, May 23, 1989

Filed:

Dec 23, 1986

Appl. No.:

6/945489

Inventors:

John R. Vollaro - Clinton NJ

Assignee:

Bell Communications Research, Inc. - Livingston NJ

International Classification:

G06F 900

US Classification:

364900

Abstract:

Circuitry, and associated methodology, in a parallel processing environment for aligning the various processing states of the autonomous processors communicating over a common bus assures that the order of execution and alignment of processing states is preserved across processors. This is effected by augmenting each processor with a state alignment network for inhibiting, within one interval of the global reference generator, generation of global reference signals. The reference generator is restarted only after all processing is completed in the order required by the allocation of tasks among the processors. To provide maximal efficiency, the state alignment network incorporated an arrangement to detect periods of delay between scheduled tasks and to automatically advance to the next immediate state requiring processing.

US Patent:

53136209, May 17, 1994

Filed:

Jul 1, 1991

Appl. No.:

7/724194

Inventors:

David M. Cohen - Morristown NJ
Bhaskarpillai Gopinath - Watchung NJ
John R. Vollaro - Clinton NJ

Assignee:

Bell Communications Research, Inc. - Livingston NJ

International Classification:

G06F 104

US Classification:

395550

Abstract:

Circuitry, and associated methodology in a parallel processing system for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus (60) provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with a global clock (31), state alignment circuit (41, 42, 43) to synchronize the processors with the global clock buffers (140, 240, 340) for storing data received off the bus, and circuitry (130, 230, 330) for selectively enabling the buffer to accept those segments of data having addresses allocated to the given processor. To ensure that processing states are aligned, each state alignment circuit inhibits incrementing of the global clock until each corresponding processor transceives necessary data over the bus. To avoid overwriting of data during bus conflicts, the buffers are arranged to store data on a first-in, first-out basis and to control the processing states and data transfer in correspondence to respective bus and processor states.