John M Hyde

US Patent:

7145370, Dec 5, 2006

Filed:

Mar 30, 2004

Appl. No.:

10/814867

Inventors:

Frédéric J. Bernard - Fuveau, FR
Christopher J. Diorio - Shoreline WA, US
Troy N. Gilliland - Newcastle WA, US
Alberto Pesavento - Seattle WA, US
Kaila G Raby - Redmond WA, US
Terry D. Hass - Ballwin MO, US
John D. Hyde - Corvallis OR, US

Assignee:

Impinj, Inc. - Seattle WA

International Classification:

H03B 1/00

US Classification:

327112, 327217

Abstract:

Circuits are provided for high-voltage switching in single-well CMOS processes.

US Patent:

7183926, Feb 27, 2007

Filed:

Apr 13, 2004

Appl. No.:

10/823991

Inventors:

Christopher J. Diorio - Shoreline WA, US
Scott Anthony Cooper - Seattle WA, US
John D. Hyde - Corvallis OR, US
Amir Sarajedini - Aliso Viejo CA, US
Kurt Eugene Sundstrom - Woodinville WA, US

Assignee:

Impinj, Inc. - Seattle WA

International Classification:

H04B 1/06
H04B 7/00
G01S 13/75

US Classification:

3405724, 455266

Abstract:

RFID tags, tag circuits, and methods adapting the reception bandwidth. A tag has a decoder for decoding a first received wireless signal subject to a reception bandwidth setting. The tag also has a selector switch for transitioning to a different setting, such as by switching to using a different filter. A subsequently received second signal is decoded subject to the new reception bandwidth setting.

US Patent:

7221596, May 22, 2007

Filed:

May 5, 2004

Appl. No.:

10/839985

Inventors:

Alberto Pesavento - Seattle WA, US
Frédéric J. Bernard - Fuveau, FR
John D. Hyde - Corvallis OR, US

Assignee:

Impinj, Inc. - Seattle WA

International Classification:

G11C 16/06

US Classification:

36518521, 36518518, 36518514, 36518528

Abstract:

A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

US Patent:

7733227, Jun 8, 2010

Filed:

Jan 17, 2007

Appl. No.:

11/624197

Inventors:

Alberto Pesavento - Seattle WA, US
Vadim Gutnik - Irvine CA, US
John D. Hyde - Corvallis OR, US

Assignee:

Impinj, Inc. - Seattle

International Classification:

G08B 13/14

US Classification:

3405721, 340 101, 34082571, 340 737

Abstract:

Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.

US Patent:

7768248, Aug 3, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/981397

Inventors:

John D. Hyde - Seattle WA, US

Assignee:

Impinj, Inc. - Seattle WA

International Classification:

G05F 3/16

US Classification:

323315, 327513, 327543

Abstract:

Embodiments of the invention describe a reference current generator circuit having a core circuit that includes a first transistor in a first current path for conduct a first current and a second transistor in a second current path for conduct a second current. The second transistor has a threshold voltage that is different from the threshold voltage of the first transistor by at least 10%. The voltage differential between the first and second transistors generate a voltage across a resistive component coupled in series with the second transistor in the second current path.

US Patent:

7768406, Aug 3, 2010

Filed:

Jun 24, 2008

Appl. No.:

12/145284

Inventors:

Charles J. T. Peach - Seattle WA, US
John D. Hyde - Corvallis OR, US

Assignee:

Impinj, Inc. - Seattle WA

International Classification:

G08B 13/14

US Classification:

3405727, 3405728, 340645, 235380

Abstract:

The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier can be constructed from serially coupled rectifier stages. One of the rectifier stages includes a backflow reduction device or a bias preservation circuit, or both, at least one of which us controlled by a signal derived from a control signal source of the tag circuit.

US Patent:

7917088, Mar 29, 2011

Filed:

Feb 2, 2007

Appl. No.:

11/670587

Inventors:

John D. Hyde - Seattle WA, US
Kurt E. Sundstrom - Seattle WA, US

Assignee:

Impinj, Inc. - Seattle WA

International Classification:

H04B 7/00

US Classification:

455 412, 455336, 3405721, 340 102, 340 1042, 340505, 340 561, 342 42, 342 44, 342 50, 235492, 235380, 327157, 327159

Abstract:

RFID tags, tag circuits, and methods are provided that reduce at least in part the distortion to received wireless signals, which is caused by interference in the environment. Two or more thresholds are used to digitize the received signal implemented by two or more demodulators. Multiple low pass and digital filters may be implemented with the demodulators, allowing removal of narrow pulses caused by the interference and reduction of beat tone amplitude.

US Patent:

8111558, Feb 7, 2012

Filed:

Oct 2, 2007

Appl. No.:

11/865777

Inventors:

Alberto Pesavento - Seattle WA, US
John D. Hyde - Corvallis OR, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G11C 11/34

US Classification:

36518528, 36518521, 36518518

Abstract:

A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

Address:

31600 126 Ave SE SPC 69, Auburn, WA 98092

Phone:

253 288-1061

VIN:

JTDKB20U577580753

Make:

TOYOTA

Model:

PRIUS

Year:

2007