John D Husher

US Patent:

6566733, May 20, 2003

Filed:

Jun 19, 2002

Appl. No.:

10/176285

Inventors:

John Durbin Husher - Santa Clara CA
Ronald L. Schlupp - Santa Clara CA

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

A01L 2900

US Classification:

257557, 257560, 257423, 257559, 257197, 257565, 257556

Abstract:

A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

US Patent:

6613974, Sep 2, 2003

Filed:

Dec 21, 2001

Appl. No.:

10/029205

Inventors:

John Durbin Husher - Los Altos Hills CA

Assignee:

Micrel, Incorporated - San Jose CA

International Classification:

H01L 3106

US Classification:

136255, 136261, 136252, 136249, 136246, 136259, 257436, 257461, 257443, 438 71, 438 73, 438 74, 438 57, 438526, 438548, 438559

Abstract:

P-type and n-type regions are defined in the first surface of a substrate upon which is formed an epitaxial layer of preferably SiâGe material, preferably capped by Si material. During epitaxy formation, dopant in the defined regions diffuses down to form p-type and n-type junctions in the Si material, and diffuses up to form p-type and n-type junctions in the SiâGe epitaxial material. Si junctions are buried beneath the surface and are surface recombination velocity effects are reduced. Photon energy striking the second substrate surface generates electron-hole pairs that experience the high bandgap of the Si materials and the low bandgap of the SiâGe epitaxy. The tandem structure absorbs photon energy from about 0. 6 eV to about 3. 5 eV and exhibits high conversion efficiency.

US Patent:

6753592, Jun 22, 2004

Filed:

Sep 6, 2002

Appl. No.:

10/236371

Inventors:

John Durbin Husher - Santa Clara CA

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 31072

US Classification:

257557, 257556, 257559, 257197, 257565, 257560, 257423

Abstract:

A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.

US Patent:

6882053, Apr 19, 2005

Filed:

Dec 28, 2001

Appl. No.:

10/034279

Inventors:

John Durbin Husher - Los Altos Hills CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L023/48
H01L023/52
H01L029/40

US Classification:

257758

Abstract:

A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system comprises providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the substrate region. Finally, the method and system includes oxidizing the slot except at the bottom of the slot and providing a metal within the slot.

US Patent:

6891249, May 10, 2005

Filed:

Jun 11, 2002

Appl. No.:

10/170156

Inventors:

John Durbin Husher - Los Altos Hills CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L027/082
H01L027/102
H01L029/70

US Classification:

257587, 257591, 257593

Abstract:

A method and system for providing a bipolar power transistor on a semiconductor device is disclosed. The method and system comprise providing a semiconductor substrate. The method and system includes providing an emitter base structure in the power device. The method and system further includes providing at least one oxidized slot through the emitter base structure and into the semiconductor substrate utilizing the highly inefficient portion of the emitter for this structure, thus wasted space is utilized to provide a power buss ground. This results in a smaller transistor for a given current. This is provided without any extra steps. This approach results in lower operating temperatures for a given current as compared to standard approaches.

US Patent:

6894393, May 17, 2005

Filed:

Dec 28, 2001

Appl. No.:

10/034067

Inventors:

John Durbin Husher - Santa Clara CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L023/48

US Classification:

257773, 257565, 438629

Abstract:

A method and system for providing a sinker on a semiconductor device is described. The method and system includes providing a substrate region and providing a buried layer and an epitaxial (EPI) layer over the substrate region. The method and system further includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the buried layer and the substrate region. The method and system finally includes oxidizing the slot except at the bottom of the slot and providing metal within the slot.

US Patent:

7002187, Feb 21, 2006

Filed:

Jun 9, 2003

Appl. No.:

10/458163

Inventors:

John Durbin Husher - Santa Clara CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 29/74
H01L 21/00
H01L 21/28

US Classification:

257109, 257117, 257127, 257135, 438 92, 438167, 438175, 438571, 438574, 438576, 438578

Abstract:

An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an epitaxial layer (EPI) on the substrate region. The diode includes a plurality of guard rings in the EPI layer and a plurality of oxidized slots. Finally, the diode includes metal within the plurality of slots to form a Buried Power Buss. A portion of the metal is completely oxide isolated from the other elements of the diode. In a second aspect, a method for manufacturing a Schottky diode comprises providing a substrate region, A buried N+ region providing an epitaxial (EPI) layer. The method also includes providing a plurality of guard rings in the EPI layer and providing a plurality of slots in the semiconductor substrate that is in contact with the EPI layer and the substrate region. The method further includes a plurality of oxidizing the slots and providing metal within the plurality of slots to form a Buried Power Buss structure. A portion of the metal is completely oxide isolated from the other elements of the diode.

US Patent:

7033901, Apr 25, 2006

Filed:

Nov 23, 2004

Appl. No.:

10/996632

Inventors:

John Durbin Husher - Santa Clara CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 21/331

US Classification:

438341, 438680

Abstract:

A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system includes providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the substrate region. Finally, the method and system includes oxidizing the slot except at the bottom of the slot and providing a metal within the slot.

Author:

John D. Husher

ISBN #:

0595405452

Author:

John D. Husher

ISBN #:

0595678092