John Patrick Dodson

Author:

John R. Dodson

ISBN #:

0195536118

Address:

4701 Wesley Rd, Amarillo, TX 79119

VIN:

1FTPW14V49KB37033

Make:

FORD

Model:

F150

Year:

2009

Address:

642 Moorside Dr, Windcrest, TX 78239

VIN:

1J8HS48P47C591232

Make:

JEEP

Model:

GRAND CHEROKEE

Year:

2007

US Patent:

6335745, Jan 1, 2002

Filed:

Feb 24, 1999

Appl. No.:

09/256376

Inventors:

Hatim Yousef Amro - Austin TX
John Paul Dodson - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 500

US Classification:

345835, 345781, 345795, 345847

Abstract:

A data processing system and method of efficiently invoking a function within a data processing system wherein the data processing system includes a processing unit, a display device that displays graphical objects in response to receipt of signals from the processing unit, and a graphical user interface (GUI) manager stored within the memory and executable by the processing unit. A graphical application is displayed within the display device. The graphical application has an associated graphical window and an associated graphical selection area. After iconizing the graphical application such that the associated graphical window and associated graphical selection area are no longer displayed, in response to a selection of the iconized graphical application, only the associated graphical selection area is opened. Thereafter, in response to a selection of a particular region among multiple regions, the function associated with the particular region is performed without displaying the associated graphical window.

US Patent:

6338124, Jan 8, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368229

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711144, 711121, 711146

Abstract:

Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy, with a coherency state and LRU position of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state and LRU position information appended to the combined operation and the snoop responses, whether an update of the LRU position and/or coherency state of a cache line corresponding to the victim within one of the snoopers is required. If so, the combined response logic selects a snooper storage device to have at least the LRU position of a respective cache line corresponding to the victim updated, and appends an update command identifying the selected snooper to the combined response. The snooper selected to be updated may be randomly chosen, selected based on LRU position of the cache line corresponding to the victim within respective storage, or selected based on other criteria.

US Patent:

6339436, Jan 15, 2002

Filed:

Dec 18, 1998

Appl. No.:

09/216549

Inventors:

Hatim Yousef Amro - Austin TX
John Paul Dodson - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300

US Classification:

345714, 345705, 345808, 345765, 345708, 707512

Abstract:

The present invention provides a method for providing user-defined dynamic help text which is displayed integrally with the application. The method includes utilizing a monitoring program to monitor a plurality of events for the application; determining if a current event of the plurality of events is a spy event; if the current event of the plurality of events is a spy event, then displaying a help text corresponding to the current event of the plurality of events. In the preferred embodiment, the method also determines if the current event of the plurality of events is a user event if the current event is not a spy event. If the current event is a user event, then the help text corresponding to the current event of the plurality of events is updated according to a user text update. The method of the present invention uses a monitoring program which allows users to create customized help texts for any application. In the preferred embodiment, the monitoring program of the present invention uses spy threads and thus is non-intrusive to the application.

US Patent:

6341336, Jan 22, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024676

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1214

US Classification:

711144, 711122, 711141

Abstract:

A cache coherency protocol uses a âTaggedâ coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

US Patent:

6343344, Jan 29, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368221

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711128, 711121, 711122, 711143

Abstract:

In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.

US Patent:

6343347, Jan 29, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368224

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711143, 711144, 711145, 711146, 711121, 711122, 711136

Abstract:

Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines appropriate responses to both the data access and the cast out/deallocate based upon the presence and coherency state of the target of the data access within a corresponding storage device, the presence and coherency state of the victim of the cast out/deallocate within the corresponding storage device, and the presence of an invalid entry within the corresponding storage device in a congruence class including both the target and the victim. The appropriate responses are âmergedâ, transmitted together in response to the combined operation as either a single response code or discrete response codes within a single response. The coherency state and LRU position of the selected victim for the cast out/deallocate portion of the combined operation may also be appended to the response to facilitate data storage management.

US Patent:

6345339, Feb 5, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024321

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1214

US Classification:

711141, 711143, 711144, 711146, 711122

Abstract:

A modified MESI cache coherency protocol is implemented within a level two (L2) cache accessible to a processor having bifurcated level one (L1) data and instruction caches. The modified MESI protocol includes two substates of the shared state, which denote the same coherency information as the shared state plus additional information regarding the contents/coherency of the subject cache entry. One substate, S , indicates that the cache entry is assumed to contain instructions since the contents were retrieved from system memory as a result of an instruction fetch operation. The second substate, S , indicates the same information plus that a snooped flush operation hit the subject cache entry while its coherency was in the first shared substate. Once the first substate is entered, the coherency state does not transition to the invalid state unless an operation designed to invalidate instructions is received. Since the contents of a cache entry in the two coherency substates are presumed to be instructions, not data, instructions within an L2 cache are not discarded as a result of snooped flushes, but are retained for possible reloads by a local processor.

US Patent:

6345340, Feb 5, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024608

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141, 711120, 711136, 711123, 711144, 711146

Abstract:

A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e. g. , DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.