John E Dickol

US Patent:

58988858, Apr 27, 1999

Filed:

Mar 31, 1997

Appl. No.:

8/829024

Inventors:

John Edward Dickol - Austin TX
Bernard Charles Drerup - Austin TX
Richard Siegmund - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1500

US Classification:

39580036

Abstract:

A method and system for executing a non-native stack-based instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of executing a set of non-native stack-access instructions is provided which includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native stack-access instructions, and part of the system memory is utilized as a stack. The instruction set convertor is utilized to convert the non-native stack-access instructions to a set of native instructions. When encountering a block of non-native stack-access instructions which include paired push and pop stack operations, the instruction set convertor produces a set of native instructions that ignores paired push and pop stack operations and retains all relevant number values in general purpose registers. The processor then processes the native instructions from the instruction set convertor, in which the immediate paired push and pop operations are eliminated.

US Patent:

58753362, Feb 23, 1999

Filed:

Mar 31, 1997

Appl. No.:

8/829022

Inventors:

John Edward Dickol - Austin TX
Bernard Charles Drerup - Austin TX
James Michael Stafford - Round Rock TX
Wendel Glenn Voigt - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9455

US Classification:

395705

Abstract:

A method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of translating non-native instructions to a set of native instructions is provided that comprises a system memory, a processor, and an instruction set convertor. The system memory is utilized to store non-native instructions and groups of unrelated native instructions. The processor is only capable of processing native instructions. The instruction set convertor, coupled between the system memory and the processor, includes a semantics table and an information table. In response to an instruction fetch from the processor for a non-native instruction in the system memory, the instruction set convertor translates the non-native instruction to a set of native instructions for the processor by accessing both the semantics table and the information table.

US Patent:

53814215, Jan 10, 1995

Filed:

Mar 5, 1992

Appl. No.:

7/846320

Inventors:

John E. Dickol - Poughkeepsie NY
Algirdas J. Gruodis - Wappingers Falls NY
Dale E. Hoffman - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128
G06F 1100

US Classification:

371 27

Abstract:

A method, and apparatus for accomplishing the method, for controlling an operation of a test pin of a per-pin semiconductor device test system. The method includes the steps of, during a test cycle, generating a plurality of timing signals, providing a test pattern comprised of M-bits, and decoding the M-bits into one of 2. sup. M first multi-bit control words. In accordance with logical states of bits of the first control word, the method selects specified ones of the timing signals and generates a stimulus signal at a test pin in accordance with the selected specified ones of the timing signals. In accordance with an aspect of the invention, the step of providing provides test patterns at a rate of (x) test patterns per second, the step of generating generates test pin stimulus signals at a rate of (y) stimulus signals per second, and wherein (y)=n(x), where (n) is an integer greater than one.

US Patent:

53768493, Dec 27, 1994

Filed:

Dec 4, 1992

Appl. No.:

7/985405

Inventors:

John E. Dickol - Poughkeepsie NY
Dinh L. Do - San Jose CA
Algirdas J. Gruodis - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 386

US Classification:

327278

Abstract:

A programmable pulse generator that uses high resolution programmable delay circuits (HRPDCs) as building blocks, each of which is capable of changing timing "on-the-fly", i. e. , modifying the programmable delay within one tester cycle and without the limitations of existing delay circuits. The pulse generator comprises a timing control array that is subdivided into three components providing coarse delay, fine delay and extra-fine delay; a plurality of timing generators respectively controlled by the timing control array, each generator further comprising a plurality of HRPDCs, programmable delay circuits, and fixed delay blocks appropriately combined to modify pulse delay and pulse edges within each cycle.

US Patent:

58988505, Apr 27, 1999

Filed:

Mar 31, 1997

Appl. No.:

8/829023

Inventors:

John Edward Dickol - Austin TX
Bernard Charles Drerup - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

395570

Abstract:

A method for executing a non-native mode-sensitive instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system as described, capable of executing a non-native mode-sensitive instruction, includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native mode-sensitive instruction. The instruction set convertor, having a Semantics Table, is utilized for converting the non-native mode-sensitive instruction to a group of native instructions by preemptively testing whether or not the mode-sensitive instruction is preceded by a mode-altering instruction within a single block, and for accessing the Semantics Table for the non-native instruction with an address according to the preemptive testing. The processor is then utilized to process the group of native instructions from the instruction set convertor.