John Wesley Buss

US Patent:

6356636, Mar 12, 2002

Filed:

Jul 22, 1998

Appl. No.:

09/120580

Inventors:

Robert I. Foster - Mesa AZ
John Michael Buss - Tempe AZ
Rodney C. Tesch - Phoenix AZ
James Douglas Dworkin - Chandler AZ
Michael J. Torla - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 930

US Classification:

380 30, 708491, 708492, 713174

Abstract:

A co-processor ( ) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier ( ) receives sixteen bit data values stored in an A/B RAM ( ) and generates a partial product. The generated partial product is summed in an adder ( ) with a previous partial product stored in a product RAM ( ). A modulo reducer ( ) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM ( ) stores the data value N that is added in a modulo reducer ( ) to the summed value. The co-processor ( ) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of as is required in the Montgomery Reduction Algorithm.

US Patent:

57269246, Mar 10, 1998

Filed:

Jul 11, 1996

Appl. No.:

8/680282

Inventors:

John Michael Buss - Tempe AZ
James Douglas Dworkin - Chandler AZ
Scott Edward Lloyd - Hoffman Estates IL
ShaoWei Pan - Schaumburg IL
Stephen L. Smith - Chandler AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

G06F 102
G06F 700
G06F 1500
G06F 750

US Classification:

364722

Abstract:

A circuit and method for computing an exponential signal x. sup. g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

US Patent:

56403364, Jun 17, 1997

Filed:

Jan 2, 1996

Appl. No.:

8/581800

Inventors:

James Douglas Dworkin - Chandler AZ
John Michael Buss - Tempe AZ

Assignee:

Motorola - Schaumburg IL

International Classification:

G06F 738
G06F 752

US Classification:

364754

Abstract:

A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable, The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript, The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.

US Patent:

62597205, Jul 10, 2001

Filed:

Dec 12, 1996

Appl. No.:

8/764344

Inventors:

John Michael Buss - Tempe AZ
James Douglas Dworkin - Chandler AZ
Stephen Lee Smith - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 169

US Classification:

375130

Abstract:

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS. 13, 14, 15, and 16).

US Patent:

55530125, Sep 3, 1996

Filed:

Mar 10, 1995

Appl. No.:

8/401515

Inventors:

John M. Buss - Tempe AZ
James D. Dworkin - Chandler AZ
Scott E. Lloyd - Hoffman Estates IL
Shao W. Pan - Schaumburg IL
Stephen L. Smith - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 102
G06F 700
G06F 1500
H03M 750

US Classification:

364722

Abstract:

A circuit and method for computing an exponential signal x. sup. g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

US Patent:

56046910, Feb 18, 1997

Filed:

Jan 31, 1995

Appl. No.:

8/381167

Inventors:

James D. Dworkin - Chandler AZ
John M. Buss - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 700
G06F 1500
G06F 102
H03M 750

US Classification:

364722

Abstract:

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, two multiplier, and two adders. The memory stores a plurality of coefficient which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

US Patent:

61821047, Jan 30, 2001

Filed:

Jul 22, 1998

Appl. No.:

9/120835

Inventors:

Robert I. Foster - Mesa AZ
John Michael Buss - Tempe AZ
Rodney C. Tesch - Phoenix AZ
James Douglas Dworkin - Chandler AZ
Michael J. Torla - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 738

US Classification:

708501

Abstract:

A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in a summer (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of. mu. as is required in the Montgomery Reduction Algorithm.

US Patent:

58527303, Dec 22, 1998

Filed:

Dec 12, 1996

Appl. No.:

8/764429

Inventors:

John Michael Buss - Tempe AZ
James Douglas Dworkin - Chandler AZ
Stephen Lee Smith - Chandler AZ

International Classification:

G06F 940

US Classification:

395588

Abstract:

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).