Jiahua Huang

US Patent:

6358760, Mar 19, 2002

Filed:

Jun 1, 2000

Appl. No.:

09/583552

Inventors:

Jiahua Huang - San Jose CA
Allison Holbrook - San Jose CA
James H. Chiang - Mountain View CA
Sunny Cherian - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

438 9, 438 6, 438 7, 438 8, 438706, 438710, 438714, 216 60

Abstract:

A silicon layer is etched using a plasma etcher equipped with an endpoint control device. CF and N are provided to the plasma etcher at lower flow rates than those typically used during fixed time etching processes. The endpoint control device monitors optical emissions from the etching chamber at a particular wavelength to detect a predetermined change in intensity. When the change in intensity is detected, the etching is terminated.

US Patent:

6383945, May 7, 2002

Filed:

Oct 29, 1999

Appl. No.:

09/430465

Inventors:

Jiahua Huang - San Jose CA
Jeffrey A. Shields - Sunnyvale CA
Allison Holbrook - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21203

US Classification:

438734, 438713, 438714, 438723, 438724, 438701, 438725, 438739, 438740, 430 5

Abstract:

An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

US Patent:

6495853, Dec 17, 2002

Filed:

Aug 10, 2000

Appl. No.:

09/636333

Inventors:

Allison Holbrook - San Jose CA
Jiahua Huang - San Jose CA
Sunny Cherian - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2906

US Classification:

257 30, 257314, 257315, 257318, 257321

Abstract:

A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.

US Patent:

6500768, Dec 31, 2002

Filed:

Oct 30, 2000

Appl. No.:

09/699531

Inventors:

Jeffrey A. Shields - Sunnyvale CA
Jiahua Huang - San Jose CA
Jean Yee-Mei Yang - Sunnyvale CA

Assignee:

Advance Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438738, 438737, 438723, 438724

Abstract:

A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.

US Patent:

6647995, Nov 18, 2003

Filed:

Jun 27, 2001

Appl. No.:

09/894569

Inventors:

Jiahua Huang - San Jose CA
Frank Mak - San Francisco CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B08B 700

US Classification:

134 13, 134 1, 134 11, 134 12, 216 62, 216 87

Abstract:

A method and system for eliminating post etch residues is disclosed. In one method embodiment, the present invention recites disposing a surface, having post etch residues adhered thereto, proximate to an electron beam source which generates electrons. The present method embodiment then recites bombarding the post etch residues with the electrons such that the post etch residues are removed from the surface to which the post etch residues were adhered.

US Patent:

6821713, Nov 23, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/085242

Inventors:

Allison Holbrook - San Jose CA
Jiahua Huang - San Jose CA
Sunny Cherian - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 726

US Classification:

430313, 430311, 438595

Abstract:

Spacer etch trim techniques are provided. The method controllably trims a multi-film stack spacer utilizing a self-limiting etch technique. The method may use a dry etch etcher with low bias power. The dry etch process may also use other modified parameters, such as gas flows and various pressures.

US Patent:

62970658, Oct 2, 2001

Filed:

Jan 12, 1999

Appl. No.:

9/229006

Inventors:

Jiahua Huang - San Jose CA
Pei-Yuan Gao - San Jose CA
Anne E. Sanderfer - Campbell CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2166

US Classification:

438 14

Abstract:

A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.

US Patent:

6013156, Jan 11, 2000

Filed:

Mar 3, 1998

Appl. No.:

9/034084

Inventors:

Allison Holbrook - San Jose CA
Jiahua Huang - San Jose CA
Aaron A. Fernandes - Oakdale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

C23F 102

US Classification:

156345

Abstract:

Apparatus for monitoring the hydrogen peroxide concentration in a sulfuric acid bath used to remove photoresist from semiconductor wafers uses the amount of bubbles in the fluid mixture to signal the addition of hydrogen peroxide. The bubbles are directly related to the hydrogen peroxide in sulfuric acid mixture. The bubbles are sensed by a light source and photoelectric sensor connected to a threshold adjustment control which controls a metering solenoid valve to add hydrogen peroxide from a reservoir to the bath when the bubbles decrease.