Ji Young Park

US Patent:

7246339, Jul 17, 2007

Filed:

Apr 8, 2005

Appl. No.:

11/101949

Inventors:

Jinyong Yuan - Cupertino CA, US
Kar Keng Chua - Penang, MY
Ji Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
H03K 17/693

US Classification:

716 16

Abstract:

Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ASIC equivalents in the library or for which possibly improved structured ASIC equivalents can now be devised. The new and/or improved structured ASIC equivalents are added to the library, preferably with version information in the case of FPGA logic functions for which more than one structured ASIC equivalent is known.

US Patent:

7386819, Jun 10, 2008

Filed:

Jul 28, 2005

Appl. No.:

11/192725

Inventors:

Jinyong Yuan - Cupertino CA, US
Ji Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 4, 716 17

Abstract:

Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e. g. , a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circuitry as a starting point for an FPGA design project. If the design project results in the same FPGA circuitry as it was intended that the structured ASIC circuitry would be functionally equivalent to, the structured ASIC circuitry has been verified and can be added to one or more libraries of structured ASIC modules that are available for use in providing structured ASIC products that are functionally equivalent to programmed FPGA products.

US Patent:

7992110, Aug 2, 2011

Filed:

May 12, 2008

Appl. No.:

12/152217

Inventors:

Jinyong Yuan - Cupertino CA, US
Ji Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 9/45

US Classification:

716103, 716100, 716101, 716102, 716106, 716107, 716116

Abstract:

Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e. g. , a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circuitry as a starting point for an FPGA design project. If the design project results in the same FPGA circuitry as it was intended that the structured ASIC circuitry would be functionally equivalent to, the structured ASIC circuitry has been verified and can be added to one or more libraries of structured ASIC modules that are available for use in providing structured ASIC products that are functionally equivalent to programmed FPGA products.

US Patent:

8076250, Dec 13, 2011

Filed:

Oct 6, 2010

Appl. No.:

12/899401

Inventors:

Nagarajan Rajagopalan - Santa Clara CA, US
Xinhai Han - Fremont CA, US
Ji Ae Park - Santa Clara CA, US
Tsutomu Kiyohara - Campbell CA, US
Sohyun Park - Santa Clara CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31

US Classification:

438763, 438712, 438585, 438396, 438710, 257E21485, 257E21409, 257288, 257530, 427255, 427 39

Abstract:

A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.

US Patent:

8283237, Oct 9, 2012

Filed:

Dec 23, 2010

Appl. No.:

12/978129

Inventors:

Nagarajan Rajagopalan - Santa Clara CA, US
Ji Ae Park - Santa Clara CA, US
Ryan Yamase - Santa Clara CA, US
Shamik Patel - Redlands CA, US
Thomas Nowak - Cupertino CA, US
Li-Qun Xia - Cupertino CA, US
Bok Hoen Kim - San Jose CA, US
Ran Ding - Sunnyvale CA, US
Jim Baldino - Portland OR, US
Mehul Naik - San Jose CA, US
Sesh Ramaswami - Saratoga CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/30
H01L 21/4763
H01L 21/44
H01L 21/31

US Classification:

438455, 438618, 438643, 438653, 438667, 438787, 438791, 257E21584

Abstract:

A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.

US Patent:

8298887, Oct 30, 2012

Filed:

Jun 25, 2010

Appl. No.:

12/824032

Inventors:

Xinhai Han - Sunnyvale CA, US
Nagarajan Rajagopalan - Santa Clara CA, US
Ji Ae Park - Santa Clara CA, US
Bencherki Mebarki - Santa Clara CA, US
Heung Lak Park - Santa Clara CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/8234

US Classification:

438237

Abstract:

Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.

US Patent:

8329575, Dec 11, 2012

Filed:

Dec 22, 2010

Appl. No.:

12/977060

Inventors:

Nagarajan Rajagopalan - Santa Clara CA, US
Ji Ae Park - Santa Clara CA, US
Ryan Yamase - Santa Clara CA, US
Shamik Patel - Redlands CA, US
Thomas Nowak - Cupertino CA, US
Li-Qun Xia - Cupertino CA, US
Bok Hoen Kim - San Jose CA, US
Ran Ding - Sunnyvale CA, US
Jim Baldino - Portland OR, US
Mehul Naik - San Jose CA, US
Sesh Ramaswami - Saratoga CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/4763
H01L 21/44
H01L 21/31

US Classification:

438643, 438653, 438789, 438792, 257E21584

Abstract:

A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.

US Patent:

8563095, Oct 22, 2013

Filed:

Mar 15, 2010

Appl. No.:

12/724396

Inventors:

Nagarajan Rajagopalan - Santa Clara CA, US
Xinhai Han - Sunnyvale CA, US
Ryan Yamase - Santa Clara CA, US
Ji Ae Park - Santa Clara CA, US
Shamik Patel - Redlands CA, US
Thomas Nowak - Cupertino CA, US
Zhengjiang “David” Cui - San Jose CA, US
Mehul Naik - San Jose CA, US
Heung Lak Park - Santa Clara CA, US
Ran Ding - Sunnyvale CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H05H 1/24
C23C 16/34

US Classification:

427579, 427 968, 427 988, 427 992, 427255393, 427255394, 427535

Abstract:

A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.