Jerry L Vandierendonck

US Patent:

39328465, Jan 13, 1976

Filed:

Sep 24, 1973

Appl. No.:

5/400438

Inventors:

Charles W. Brixey - Missouri City TX
Glenn A. Hartsell - Dallas TX
Jerry L. Vandierendonck - Santa Cruz CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 314

US Classification:

3401725

Abstract:

An electronic calculator system of the type having a keyboard input and a visual display is implemented in MOS/LSI semiconductor chips having a data memory, an arithmetic unit, a read-only-memory for storing instruction words, and control circuitry for operating the system in response to keyboard inputs by selecting addresses for instructions from the read-only-memory, all of which is located in monolithic semiconductor units. A technique is provided for turning off the display after a selected time period by holding an instruction word in an instruction register while repeatedly incrementing an address register for the ROM until it overflows, then branching to an address defined in such instruction word. This is repeated until the selected time period is reached.

US Patent:

39848167, Oct 5, 1976

Filed:

Aug 25, 1975

Appl. No.:

5/607525

Inventors:

Michael J. Cochran - Richardson TX
Jerry L. Vandierendonck - Santa Cruz CA

Assignee:

Texas Instruments, Inc. - Dallas TX

International Classification:

G06F 302

US Classification:

3401725

Abstract:

An electronic portable calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. The calculator system utilizes a plurality of output terinals on the primary MOS/LSI chip for selectively addressing in timed coded sequence an array of peripheral MOS/LSI chips providing for expanded register and memory capacity and for output printing. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.

US Patent:

39874168, Oct 19, 1976

Filed:

Sep 24, 1973

Appl. No.:

5/400437

Inventors:

Jerry L. Vandierendonck - Santa Cruz CA
Roger J. Fisher - Houston TX
Glenn A. Hartsell - Dallas TX

International Classification:

G06F 300

US Classification:

3401725

Abstract:

An electronic calculator system of the type having a keyboard input and a visual display readout is implemented in MOS/LSI semiconductor chips having a data memory, an arithmetic unit, a read-only-memory for storing instruction words, and control circuitry for operating the system in response to keyboard inputs, all in monolithic semiconductor units. The keyboard and display are scanned by timing signals generated in the semiconductor unit by a register associated with the data memory.

US Patent:

40042804, Jan 18, 1977

Filed:

Jul 7, 1975

Appl. No.:

5/593594

Inventors:

Jerry L. Vandierendonck - Santa Cruz CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1300

US Classification:

3401725

Abstract:

Disclosed is an expandable calculator system of the type implemented on semiconductor chips providing additional data storage registers for increasing data storage capacity of the basic system. A basic calculator system comprising two semiconductor chips is provided with additional semiconductor chips each providing a plurality of separately addressable registers for storing data, to thereby increase the data storage capacity of the two-chip system. First and second control signals synchronize the internal timing of the external register chips and also enable communication to the external chips. The data system has 10 registers on each of the additional semiconductor chips which are addressed by means responsive to instructions communicated via the data transmission path.