Jerry D. Holmes - Dallas TX Hatcher E. Chalkley - Carrollton TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 2706
US Classification:
375 97
Abstract:
A Global Position System (GPS) receiver is disclosed which includes an RF converter and quadrature digitizer implemented in hardware and a signal processor including a computer, code generator and preprocessor. The preprocessor has a divide by 1,2,3 divider for controlling the code generator so as to provide I,Q early, prompt and late digital signals of 0. 5 chip separations to the computer for tracking code phase, carrier phase/frequency and signal amplitude. This structure eliminates the need for numerically controlled oscillators implemented in hardware while maintaining accurate performance.
Gps System And Method For Deriving Pointing Or Attitude From A Single Gps Receiver
Phillip W. Ward - Dallas TX H. Logan Scott - The Colony TX Jerry D. Holmes - Colorado Springs CO Leonard J. LaPadula - Carrollton TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04B 7185 G01S 502
US Classification:
342357
Abstract:
A GPS single-receiver pointing/attitude system derives pointing/attitude measurements by correlating a selected GPS code (either P or C/A), recovered from GPS navigation signals using a single GPS receiver with multiple GPS antennas (a reference antenna and at least two slave antennas for pointing or three for attitude). For a two antenna pointing application, the GPS receiver (FIG. 4) includes, for each receiver channel, the incoming GPS signals are applied to three code correlators (72-75) assigned to the reference antenna, and three code correlators (76-77) assigned to the slave antenna, which provide corresponding reference and slave I and Q correlation outputs. The single-receiver pointing technique involves: (a) using the reference I and Q correlation outputs to establish a conventional reference antenna tracking loop; and (b) processing the reference and slave I and Q correlation outputs (using differential carrier doppler phase or code phase measurements) to determine phase differences from which pointing can be computed.
Jerry D. Holmes - Dallas TX Benjamin L. Lowe - Huntsville AL Samuel D. Moore - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04B 116
US Classification:
325347
Abstract:
An SWD structure is employed in an FM receiver for signal demodulation and band limiting. An FM signal is applied to the input of an SWD patterned for bandwidth limitation. Two SWD output channels characterized by predetermined differential delays of the modulated input signal are amplitude limited and mixed to produce an audio modulation component.
Jerry D. Holmes - Dallas TX Charles R. Johnson - Garland TX Allen S. Jones - Dallas TX Charles R. Hewes - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04L 100
US Classification:
325321
Abstract:
An improved spread spectrum communication system having a transmitter subsystem and a receiver subsystem is disclosed. The transmitter subsystem comprises a data source of 50 bps rate which is modulo-2 added to a C/A (clear/acquisition) code of 1,023K chips/sec in an EXCLUSIVE OR gate, phase modulated on a carrier signal at about 154 f. sub. o where f. sub. o = 10. 23 MHz in a phase shift keying modulator and transmitted. The receiver subsystem comprises an antenna for receiving the phase modulated signal, a plurality of filter/amplifier mixer stages for reducing the phase modulated signal to baseband, an in-phase CCD matched filter channel and a quadrature phase CCD matched filter channel for determining the presence of the C/A code and the phase of the incoming C/A code for synchronizing a replica of the C/A code with the incoming C/A code, a mixer for beating the replica C/A code signal with the C/A code signal, a Costas loop for automatic phase control, a sampler for sampling the baseband signal, an integrator for integrating the sampled signals, and a clocked comparator for comparing the integrated signals with a zero voltage at a 50Hz rate to demodulate the data code. Two embodiments of the CCD matched filter are disclosed. The first comprises a CCD having a length equal to five times the number of stages for each period of the C/A code.