Jerome C Huck

Author:

Jerome C. Huck

ISBN #:

0818688572

US Patent:

6370639, Apr 9, 2002

Filed:

Oct 10, 1998

Appl. No.:

09/169482

Inventors:

Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA
Guillermo Juan Rozas - Los Gatos CA

Assignee:

Institute for the Development of Emerging Architectures L.L.C. - Cupertino CA

International Classification:

G06F 9312

US Classification:

712222, 712224, 712228, 712235, 712239

Abstract:

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

US Patent:

6393544, May 21, 2002

Filed:

Oct 31, 1999

Appl. No.:

09/430793

Inventors:

William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
Gary N. Hammond - Fort Collins CO
James O. Hays - San Jose CA
Jerome C. Huck - Palo Alto CA
Jonathan K. Ross - Woodinville WA
Sunil Saxena - Sunnyvale CA
Koichi Yamada - San Jose CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 1200

US Classification:

711220, 711203, 711216, 711206, 711221, 711202

Abstract:

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A âshort formatâ page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single âlong formatâ page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2 bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2 bytes long.

US Patent:

6408380, Jun 18, 2002

Filed:

May 21, 1999

Appl. No.:

09/316446

Inventors:

Jerome C. Huck - Palo Alto CA
Glenn T. Colon-Bonet - Ft. Collins CO
Alan H. Karp - Palo Alto CA
David A. Fotland - San Jose CA
Dean A. Mulla - San Jose CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 9312

US Classification:

712225, 711149, 712200

Abstract:

Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.

US Patent:

6430657, Aug 6, 2002

Filed:

Oct 12, 1998

Appl. No.:

09/170137

Inventors:

Millind Mittal - Palo Alto CA
Martin J. Whittaker - Cupertino CA
Gary N. Hammond - Campbell CA
Jerome C. Huck - Palo Alto CA

Assignee:

Institute for the Development of Emerging Architecture L.L.C. - Cupertino CA

International Classification:

G06F 1210

US Classification:

711138, 711207, 711143, 711118

Abstract:

Atomic memory operations are provided by using exportable âfetch and addâ instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present invention, a CPU includes a default control register that includes IA-32 lock check enable bit (LC) that when set to â1â, causes an IA-32 atomic memory reference to raise an IA-32 intercept lock fault. An IA-32 intercept lock fault handler branches to appropriate code to atomically emulate the instruction. Furthermore, the present invention defines an exportable fetch and add (FETCHADD) instruction that reads a memory location indexed by a first register, places the contents read from the memory location into a second register, increments the value read from the memory location, and stores the sum back to the memory location. Associated with each virtual memory page is a memory attribute that can assume a state of âcacheable using a write-back policyâ (WB), âuncacheableâ (UC), or âuncacheable and exportableâ (UCE). When a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to WB, the FETCHADD is atomically executed by the CPU by obtaining exclusive use of the cache line containing the memory location.

US Patent:

6505296, Jan 7, 2003

Filed:

Mar 8, 2000

Appl. No.:

09/521160

Inventors:

Dale C. Morris - Menlo Park CA
Jonathan K. Ross - Woodinville WA
James O. Hays - San Jose CA
Jerome C. Huck - Palo Alto CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 942

US Classification:

712244, 710261, 710269

Abstract:

A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

US Patent:

6578059, Jun 10, 2003

Filed:

Oct 10, 1998

Appl. No.:

09/169669

Inventors:

Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 748

US Classification:

708496, 712222

Abstract:

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

US Patent:

6643769, Nov 4, 2003

Filed:

Aug 23, 2000

Appl. No.:

09/644315

Inventors:

Jerome Huck - Palo Alto CA
Carol L. Thompson - San Jose CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 932

US Classification:

712227, 712239, 712230, 714 35, 714 38, 717124, 717131

Abstract:

The system of the present invention utilizes memory for storing a computer program and processing circuitry for executing instructions of the computer program. In particular, the computer program includes at least one branch instruction and a set of code that is to be selectively enabled or disabled. The branch instruction includes an address identifier identifying a memory address to which the processing circuitry may branch when executing the branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry executes the branch instruction. In executing the branch instruction, the processing circuitry, depending on the value of the mode indicator, branches to the address identified by address identifier or branches to a different address.

US Patent:

6654877, Nov 25, 2003

Filed:

Aug 23, 2000

Appl. No.:

09/644435

Inventors:

Jerome Huck - Palo Alto CA
Carol L. Thompson - San Jose CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 944

US Classification:

712229, 712227, 712236, 717128, 717130, 717141

Abstract:

A system of the present invention utilizes memory for storing a computer program and processing circuitry for processing and executing instructions of the computer program. In particular, the computer program includes a set of code and an unconditional branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry receives and processes the unconditional branch instruction. When the set of code is disabled, the processing circuitry executes the unconditional branch instruction based on the mode indicator, thereby preventing execution of the set of code. However, when the set of code is enabled, the processing circuitry refrains from executing the unconditional branch instruction based on the mode indicator and executes the set of code. Thus, execution of the set of code is selectively enabled based on the status of the mode indicator.