Jennifer L Church

US Patent:

20230099965, Mar 30, 2023

Filed:

Sep 29, 2021

Appl. No.:

17/449381

Inventors:

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Praveen Joseph - White Plains NY, US
Jennifer Church - Albany NY, US

International Classification:

H01L 23/532
H01L 21/768

Abstract:

Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.

US Patent:

20210325784, Oct 21, 2021

Filed:

Apr 16, 2020

Appl. No.:

16/851034

Inventors:

- Armonk NY, US
Jennifer Church - Troy NY, US
Nelson Felix - Slingerlands NY, US
Ekmini Anuja De Silva - Slingerlands NY, US

International Classification:

G03F 7/09
G03F 7/20

Abstract:

An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80.

US Patent:

20210149298, May 20, 2021

Filed:

Nov 19, 2019

Appl. No.:

16/688657

Inventors:

- Armonk NY, US
Jing Guo - Niskayuna NY, US
Jennifer Church - Troy NY, US
Dario Goldfarb - Dobbs Ferry NY, US

International Classification:

G03F 7/004
H01L 21/027

Abstract:

A metal brush layer is provided. The metal brush layer includes a polymer backbone including at least one grafting unit, G, attached to the polymer backbone, and a plurality of metal-containing moieties, M, attached to the polymer backbone.

US Patent:

20200274066, Aug 27, 2020

Filed:

Feb 27, 2019

Appl. No.:

16/286995

Inventors:

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Jennifer Church - Troy NY, US

International Classification:

H01L 45/00
H01L 27/22
H01L 43/02
H01L 43/12
H01L 27/24

Abstract:

A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.

US Patent:

20200161540, May 21, 2020

Filed:

Nov 19, 2018

Appl. No.:

16/194443

Inventors:

- Armonk NY, US
Ekmini Anuja de Silva - Singerlands NY, US
Jennifer Church - Troy NY, US
Luciana Meli Thompson - Albany NY, US

International Classification:

H01L 43/12
H01L 21/02
H01L 43/02
H01L 27/22

Abstract:

A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.

US Patent:

20200144107, May 7, 2020

Filed:

Nov 5, 2018

Appl. No.:

16/180834

Inventors:

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Jennifer Church - Troy NY, US
Luciana Meli Thompson - Albany NY, US

International Classification:

H01L 21/768
H01L 23/532
H01L 23/522
H01L 23/528

Abstract:

A method includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer. The vias are filled with a first metallic material. A cap layer is deposited on a top surface of the first insulating layer and a top surface of the one or more vias and a second insulating layer is deposited on a top surface of the cap layer. One or more openings are formed in the second insulating layer and the cap layer. A self-assembled monolayer is formed on an exposed top surface of the first metallic material in the one or more vias. A barrier layer is formed on at least the exposed surface of the one or more openings. The self-assembled monolayer is removed and the one or more openings are filled with a second metallic material.