Jeffrey G Herbert

US Patent:

6366944, Apr 2, 2002

Filed:

Jan 15, 1999

Appl. No.:

09/231131

Inventors:

Razak Hossain - Bridgewater NJ 08807
Jeffrey Charles Herbert - Nazareth PA 18064

International Classification:

G06F 752

US Classification:

708628, 708 7

Abstract:

An apparatus for performing signed and unsigned multiplication is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell, and a selector coupled to each of the computation cell and the compressor. As disclosed, the selector selects and passes either a standard partial product term or an inverse thereof to the compressor, based on whether signed or unsigned multiplication is being performed, respectively, while the compressor compresses the received partial product terms into a pair of partial product terms.

US Patent:

48498050, Jul 18, 1989

Filed:

Nov 20, 1987

Appl. No.:

7/123199

Inventors:

Jeffrey C. Herbert - Lansdale PA
Kenneth M. Schlesier - Stockton NJ

Assignee:

General Electric Company - Fairfield CT

International Classification:

H01L 2978
H01L 2702
H01L 2712
H01L 2934

US Classification:

357 237

Abstract:

A SOI integrated circuit includes a plurality of islands of single crystalline silicon on a surface of a substrate of an insulating material. Each of the silicon islands contains an electrical component, such as a MOS transistor. A layer of silicon oxide is on the surface of the substrate between the islands and is slightly spaced, at least about 0. 1 micrometers, from each of the silicon islands. A line of a conductive material, such as conductive polycrystalline silicon, extends over the silicon islands and between the silicon islands over the silicon oxide layer. The silicon oxide layer isolates the conductive line from the substrate so that any photocurrent generated in the substrate as a result of the integrated circuit being exposed to radiation will not flow through the conductive line to disrupt the circuit.

US Patent:

61345768, Oct 17, 2000

Filed:

Apr 30, 1998

Appl. No.:

9/071383

Inventors:

Razak Hossain - Bridgewater NJ
Roland A. Bechade - Branchburg NJ
Jeffrey C. Herbert - Nazareth PA

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 750

US Classification:

708710

Abstract:

A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.

Author:

Jeffrey G. Herbert

ISBN #:

0788400630

Author:

Jeffrey G. Herbert

ISBN #:

0788401394

Author:

Jeffrey G. Herbert

ISBN #:

0788404199

Author:

Jeffrey G. Herbert

ISBN #:

0788406167

Author:

Jeffrey G. Herbert

ISBN #:

0788410393

Author:

Jeffrey G. Herbert

ISBN #:

0788408917

Author:

Jeffrey G. Herbert

ISBN #:

0788415042

Author:

Jeffrey G. Herbert

ISBN #:

0788417290