Jeffrey R Herbert

US Patent:

6366944, Apr 2, 2002

Filed:

Jan 15, 1999

Appl. No.:

09/231131

Inventors:

Razak Hossain - Bridgewater NJ 08807
Jeffrey Charles Herbert - Nazareth PA 18064

International Classification:

G06F 752

US Classification:

708628, 708 7

Abstract:

An apparatus for performing signed and unsigned multiplication is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell, and a selector coupled to each of the computation cell and the compressor. As disclosed, the selector selects and passes either a standard partial product term or an inverse thereof to the compressor, based on whether signed or unsigned multiplication is being performed, respectively, while the compressor compresses the received partial product terms into a pair of partial product terms.

US Patent:

61483168, Nov 14, 2000

Filed:

May 5, 1998

Appl. No.:

9/072774

Inventors:

Jeffrey Charles Herbert - Nazareth PA
Jason F. Gouger - Shawnee-On-Delaware PA
Razak Hossain - Bridgewater NJ

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 742
G06F 738
G06F 700

US Classification:

708505

Abstract:

An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU includes a shifter, a bypass datapath, and a bypass multiplexer. The shifter receives an operand input and a control input, and shifts the operand input in accordance with the control input. The bypass datapath bypasses the operand input around the shifter. The bypass multiplexer is coupled to the shifter and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable an integer addition if the operand is an integer operand, and selects the shifter to enable a floating point addition or floating point to integer conversion if the operand is a floating point operand. In an alternate embodiment, the FPU includes an alignment unit, an arithmetic logic unit (ALU), a bypass datapath, and a bypass multiplexer. The alignment unit receives a first input and a second input, and aligns them.

US Patent:

61345768, Oct 17, 2000

Filed:

Apr 30, 1998

Appl. No.:

9/071383

Inventors:

Razak Hossain - Bridgewater NJ
Roland A. Bechade - Branchburg NJ
Jeffrey C. Herbert - Nazareth PA

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 750

US Classification:

708710

Abstract:

A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.

US Patent:

61956724, Feb 27, 2001

Filed:

Aug 31, 1998

Appl. No.:

9/144599

Inventors:

Jason F. Gouger - Shawnee-on-Delaware PA
Jeffrey Charles Herbert - Nazareth PA
Razak Hossain - Bridgewater NJ

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 500

US Classification:

708204

Abstract:

An improved method and apparatus for saturation detection in floating point to integer conversions is described. A floating point number is tested for saturation conditions based on an integer field size. From testing the saturation conditions on the floating point number, the present invention predicts whether a floating point number can be converted into an integer value having the given integer field size, or whether the integer field would be saturated. In one embodiment, the saturation conditions are tested on the floating point number in parallel with a floating point to integer conversion.

US Patent:

6148315, Nov 14, 2000

Filed:

Apr 30, 1998

Appl. No.:

9/071358

Inventors:

Jeffrey C. Herbert - Nazareth PA
Razak Hossain - Bridgewater NJ
Roland A. Bechade - Branchburg NJ

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 750
G06F 501

US Classification:

708505

Abstract:

An improved floating point unit is disclosed. The floating point unit includes a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand. The combined adder-shifter includes an adder portion that operates to generate a number of sum bits for exponent difference between the two floating point operands. The adder portion favors generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits. The combined adder-shifter also includes a shifter portion that operates to shift the mantissa portion of the at least one floating point operand in accordance with the sum bits.

Author:

Jeffrey G. Herbert

ISBN #:

0788400630

Author:

Jeffrey G. Herbert

ISBN #:

0788401394

Author:

Jeffrey G. Herbert

ISBN #:

0788404199

Author:

Jeffrey G. Herbert

ISBN #:

0788406167

Author:

Jeffrey G. Herbert

ISBN #:

0788410393

Author:

Jeffrey G. Herbert

ISBN #:

0788408917

Author:

Jeffrey G. Herbert

ISBN #:

0788415042

Author:

Jeffrey G. Herbert

ISBN #:

0788417290