Jean Hsiu-Chin Yang

US Patent:

6362051, Mar 26, 2002

Filed:

Aug 25, 2000

Appl. No.:

09/648361

Inventors:

Jean Yang - Sunnyvale CA
Yider Wu - San Jose CA
Hidehiko Shiraiwa - San Jose CA
Mark Ramsbey - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 21336

US Classification:

438261, 438444, 438448, 438585, 438264, 438239, 438762

Abstract:

A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

US Patent:

6395654, May 28, 2002

Filed:

Aug 25, 2000

Appl. No.:

09/648077

Inventors:

Jean Yang - Sunnyvale CA
Yider Wu - San Jose CA
Hidehiko Shiraiwa - San Jose CA
Mark Ramsbey - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 21225

US Classification:

438954, 438306

Abstract:

A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

US Patent:

6399984, Jun 4, 2002

Filed:

Jun 15, 2001

Appl. No.:

09/882242

Inventors:

Yider Wu - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Yu Sun - Saratoga CA
Tuan Duc Pham - Santa Clara CA
Jean Y. Yang - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257316, 257314

Abstract:

A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

US Patent:

6403420, Jun 11, 2002

Filed:

Jul 28, 2000

Appl. No.:

09/627664

Inventors:

Jean Yang - Sunnyvale CA
Yider Wu - San Jose CA
Mark Ramsbey - Sunnyvale CA
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438261, 438257, 438264, 438514

Abstract:

A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.

US Patent:

6417082, Jul 9, 2002

Filed:

Aug 30, 2000

Appl. No.:

09/651684

Inventors:

Yider Wu - San Jose CA
Jean Yang - Sunnyvale CA
Hidehiko Shiraiwa - San Jose CA
Mark E. Ramsbey - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 21425

US Classification:

438528, 438520, 438585

Abstract:

A process for making a semiconductor structure comprises implanting nitrogen through a layer comprising SiO into a substrate comprising Si, wherein the layer is on the substrate, and wherein the layer is from about 30 to about 300 thick.

US Patent:

6436768, Aug 20, 2002

Filed:

Jun 27, 2001

Appl. No.:

09/893279

Inventors:

Jean Yee-Mei Yang - Sunnyvale CA
Mark T. Ramsbey - Sunnyvale CA
Emmanuil Manos Lingunis - San Jose CA
Yider Wu - San Jose CA
Tazrien Kamal - San Jose CA
Yi He - Sunnyvale CA
Edward Hsia - Saratoga CA
Hidehiko Shiraiwa - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

International Classification:

H01L 21336

US Classification:

438266, 438257

Abstract:

One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

US Patent:

6440797, Aug 27, 2002

Filed:

Sep 28, 2001

Appl. No.:

09/966702

Inventors:

Yider Wu - Campell CA
Jean Yee-Mei Yang - Sunnyvale CA
Mark Ramsbey - Sunnyvale CA
Emmanuel H. Lingunis - San Jose CA
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438261, 438954, 438558

Abstract:

A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

US Patent:

6441398, Aug 27, 2002

Filed:

Jun 27, 2001

Appl. No.:

09/894670

Inventors:

Jean Yang - Palo Alto CA
Ian Dudley - Santa Clara CA
Khoi Phan - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2358

US Classification:

257 48, 438 14, 438 16, 738658, 382145

Abstract:

A method for contact hole formation and inspection during integrated circuit fabrication is disclosed. The method includes defining tolerances for one or more contact hole formation processes, and then performing the formation processes to create at least one contact hole. After at least one of the formation processes is performed, a waveform is generated for the contact hole. A critical dimension (CD) and an edge width value are then generated for the contact hole from the waveform. The CD and the edge width value are then compared to the tolerances to detect and correct variations in the formation process. In a further aspect of the present invention, the edge width is compared to a predetermined limit to automatically detect contact holes having sloped sidewalls.