Jason D Hibbeler

US Patent:

6970809, Nov 29, 2005

Filed:

Aug 29, 2001

Appl. No.:

09/941306

Inventors:

Cheng A. Feng - Woodstock NY, US
Jason D. Hibbeler - Williston VT, US
Judith K. Ingles - Poughkeepsie NY, US
Jhy-Chun Wang - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F019/00

US Classification:

702186, 716 4, 714 30, 714 38, 714 39, 714 47

Abstract:

A system and method for configuring a plurality of monitors, which are contained within a complex circuit, to monitor a valid combination of events within the complex circuit. Each monitor of the complex circuit is only able to monitor a subset of the total set of events which may be monitored. The present invention allows a user to select valid associations between events and monitors, and then processes those selected associations for configuration of the complex circuit. The selected associations may be stored and reused in the future.

US Patent:

7062729, Jun 13, 2006

Filed:

Sep 22, 2004

Appl. No.:

10/946677

Inventors:

Michael S. Gray - Fairfax VT, US
Jason D. Hibbeler - Williston VT, US
Gustavo E. Tellez - Essex Junction VT, US
Robert F. Walker - St. George VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 3, 716 11

Abstract:

A method () and system () for optimizing a circuit layout based on layout constraints () and objectives (). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.

US Patent:

7093234, Aug 15, 2006

Filed:

Aug 24, 2001

Appl. No.:

09/939005

Inventors:

Jason D. Hibbeler - Williston VT, US
Jhy-Chun Wang - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 9/45

US Classification:

717124, 717127, 717128

Abstract:

A method, and computer readable medium for the dynamic CPU (Central Processing Unit) usage and function call tracing on a target application. The setup of the tracing uses a -pg like solution, and is implemented using the DPCL (Dynamic Probe Class Library). The output is presented in a gmon. out format, which allows the use of popular analysis tools. The program being traced need not be recompiled or re-linked. This is particularly important if the source code is not available. The dynamic feature allows for different choices of profiling and the choice can even be changed once the target application is running.

US Patent:

7120887, Oct 10, 2006

Filed:

Jan 16, 2004

Appl. No.:

10/707845

Inventors:

Michael S. Gray - Fairfax VT, US
Jason D. Hibbeler - Williston VT, US
Kevin W. McCullen - Essex Junction VT, US
Robert F. Walker - St. George VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 10, 716 4, 716 5, 716 11

Abstract:

A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

US Patent:

7188322, Mar 6, 2007

Filed:

Feb 25, 2005

Appl. No.:

10/906591

Inventors:

John M. Cohn - Richmond VT, US
Jason Hibbeler - Williston VT, US
Anthony K. Stamper - Williston VT, US
Jed H. Rankin - Richmond VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 2, 716 19, 716 20, 716 21

Abstract:

A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

US Patent:

7257783, Aug 14, 2007

Filed:

Dec 9, 2004

Appl. No.:

10/905008

Inventors:

Robert J. Allen - Jericho VT, US
Cam V. Endicott - Essex Junction VT, US
Jason D. Hibbeler - Williston VT, US
Kevin W. McCullen - Essex Junction VT, US
Rani Narayan - San Jose CA, US
Robert F. Walker - St. George VT, US
Xin Yuan - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 3, 716 11

Abstract:

A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.

US Patent:

7260790, Aug 21, 2007

Filed:

Apr 27, 2004

Appl. No.:

10/709292

Inventors:

Robert J. Allen - Jericho VT, US
Michael S. Gray - Fairfax VT, US
Jason D. Hibbeler - Williston VT, US
Mervyn Yee-Min Tan - South Burlington VT, US
Robert F. Walker - St. George VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 2, 716 10

Abstract:

A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.

US Patent:

7290226, Oct 30, 2007

Filed:

Apr 4, 2005

Appl. No.:

10/907496

Inventors:

Anthony Correale, Jr. - Raleigh NC, US
Jason D. Hibbeler - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 2, 716 6, 716 12

Abstract:

Methods, systems and program products are disclosed that prioritize each target via for via redundancy based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic, and attempt to add a redundant via to each target via based on the prioritization. The invention improves overall yield and reduces timing sensitivity to AC-related defects.