Jashojiban J Banik

US Patent:

55597459, Sep 24, 1996

Filed:

Sep 15, 1995

Appl. No.:

8/529016

Inventors:

Jashojiban Banik - Aloha OR
Anne Meixner - Aloha OR
Glenn F. King - Aloha OR
Doug Guddat - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700
G11C 2900

US Classification:

365201

Abstract:

A test circuit and method for testing a memory cell in a static random access memory. The memory cell is coupled to a bit line and a complementary bit line. The test circuit includes a charging device coupled to selectively charge one of the bit line or the complementary bit line and a discharging device coupled to selectively discharge the other of the bit line and the complementary bit line. To test a memory cell containing the first value, the test circuit performs a weak write of the second value to the memory cell. The weak write overwrites the first value contained in the memory cell with the second value if the memory cell is defective. The memory cell retains the first value if functioning properly.

US Patent:

55792545, Nov 26, 1996

Filed:

Jun 6, 1995

Appl. No.:

8/471287

Inventors:

Sudarshan Kumar - Aloha OR
Jashojiban Banik - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 750
G06F 738

US Classification:

364788

Abstract:

An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.

US Patent:

56569629, Aug 12, 1997

Filed:

Dec 18, 1996

Appl. No.:

8/768792

Inventors:

Jashojiban Banik - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 3037
H03K 3356

US Classification:

327202

Abstract:

A master-slave flip-flop circuit is described. The flip-flop circuit comprises of a master circuit capable of storing and transmitting a signal and a slave circuit capable of storing and transmitting the signal. The flip-flop circuit also comprises of a bypass circuit capable of transmitting the signal to an output of the flip-flop.

US Patent:

55086489, Apr 16, 1996

Filed:

Aug 1, 1994

Appl. No.:

8/283643

Inventors:

Jashojiban Banik - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 3356

US Classification:

327203

Abstract:

A differential latch circuit which places very little capacitance on the clock line is described. The invented differential latch circuit utilizes differential data signals, and thus, has two data lines. The transfer portion of the latch receives the differential data signals and passes them to the storage portion responsive to a control signal. The storage portion stores and outputs the differential data signals. In a first embodiment, each data line in the transfer portion comprises a single transistor pass gate for selectively passing one of the differential data signals responsive to the control signal, which is coupled to the gate terminals of both pass gates.

US Patent:

57421900, Apr 21, 1998

Filed:

Jun 27, 1996

Appl. No.:

8/670486

Inventors:

Jashojiban Banik - Aloha OR
Keng L. Wong - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 700

US Classification:

327152

Abstract:

A method and apparatus for clocking latches in a system having both pulse latches and two-phase latches includes a clock generating circuit for generating a local clock signal based on a global clock signal and also includes a pulse generating circuit for generating a pulse signal based on the global clock signal. A clock signal path transfers the local clock signal from the clock generating circuit to both a first portion and a second portion of the two-phase latch. Similarly, a pulse signal path transfers the pulse signal from the pulse generating circuit to the pulse latch. According to one embodiment, the pulse generating circuit and the clock generating circuit have paths of equal delay, thereby causing a rising edge of the local clock signal to occur at the same time as a rising edge of the pulse signal.

US Patent:

57421927, Apr 21, 1998

Filed:

Jun 15, 1995

Appl. No.:

8/491489

Inventors:

Jashojiban Banik - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 501

US Classification:

327166

Abstract:

A pulse generating circuit includes a first portion and a second portion. The first portion is coupled to a control signal and a first signal, and generates the rising edge of a pulse signal in response to the control signal transitioning to a first state. The second portion receives the rising edge of the pulse signal and causes the first signal to transition to a second state in response to the rising edge of the pulse. The transitioning of the first signal to the second state causes the first portion to generate a falling edge of the pulse signal.

US Patent:

61857203, Feb 6, 2001

Filed:

Jun 19, 1998

Appl. No.:

9/100075

Inventors:

Jashojiban Banik - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 2

Abstract:

An apparatus includes a master latch of a master/slave flip-flop, wherein the master latch includes a first data output. The apparatus also includes a logic coupled to receive the first data output, wherein the logic includes a second data output without using a slave latch of a master/slave flip-flop, and a non-slave latch coupled to receive the second data output.

US Patent:

54714141, Nov 28, 1995

Filed:

Mar 17, 1993

Appl. No.:

8/032607

Inventors:

Sudarshan Kumar - Aloha OR
Jashojiban Banik - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 750
G06F 738

US Classification:

364788

Abstract:

An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.