Jaroslav J Hynecek

US Patent:

6369413, Apr 9, 2002

Filed:

Nov 5, 1999

Appl. No.:

09/434451

Inventors:

Jaroslav Hynecek - Richardson TX

Assignee:

Isetex, Inc. - Allen TX

International Classification:

H01L 27148

US Classification:

257215, 257216, 257218

Abstract:

Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

US Patent:

6459077, Oct 1, 2002

Filed:

Sep 15, 1999

Appl. No.:

09/395994

Inventors:

Jaroslav Hynecek - Richardson TX

Assignee:

Dalsa, Inc. - Waterloo

International Classification:

H04N 314

US Classification:

2502081, 2502141, 257251, 348295, 377 57

Abstract:

A TDI sensor includes a bias charge voltage circuit, a reset voltage circuit, a bucket brigade column having a plurality of nodes, and a plurality of pinned photodiodes. Each photodiode is formed integral with a corresponding node of the bucket brigade column. The bucket brigade column is coupled between the bias charge voltage circuit at an initial node and the reset voltage circuit at a final node. The bucket brigade column includes a plurality of first phase clock conductors, and a plurality of second phase clock conductors, and the first and second phase clock conductors are interdigitated and formed of poly-crystalline silicon. The TDI sensor is formed in a substrate of a first conductivity type, and a cathode of each pinned photodiode is formed of a second conductivity type, and each pinned photodiode includes a pinning layer of the first conductivity type.

US Patent:

6518607, Feb 11, 2003

Filed:

Jun 6, 2001

Appl. No.:

09/874033

Inventors:

Jaroslav Hynecek - Richardson TX

Assignee:

Isetex, Inc. - Allen TX

International Classification:

H01L 27148

US Classification:

257239, 257229, 257249

Abstract:

A new High Dynamic Range charge detection concept useful for CCD and Active Pixel CMOS image sensors uses at least one transistor operating in a punch through mode for the charge detection node reset. The punch through operation significantly reduces the reset feed through which leads to a higher voltage swing available on the node for the signal. This in turn allows building smaller and thus more sensitive charge detection nodes. The undesirabe artifacts, associated with the incomplete reset that are induced by the punch through operation, are completely removed by incorporating the CDS signal processing method into the signal processing chain. The incomplete reset artifact removal by the CDS technique is extended to all other resetting concepts that are modeled by a large reset time constant. The punch through concept is suitable for resetting Floating Diffusion charge detection nodes as well as Floating Gate charge detection nodes.

US Patent:

6522355, Feb 18, 2003

Filed:

Apr 7, 1998

Appl. No.:

09/056678

Inventors:

Jaroslav Hynecek - Richardson TX
Russell J. Austin - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 964

US Classification:

348245, 348243

Abstract:

A method of compensating for nonuniformities in an image sensor includes: providing an image sensing device ; measuring test pixel signals from the image sensing device during a test mode; determining which test pixel signals are greater than a fixed threshold level S ; and calculating nonuniformity coefficients for the pixels having test pixel signals greater than the fixed threshold level S.

US Patent:

6580106, Jun 17, 2003

Filed:

Jan 10, 2002

Appl. No.:

10/043419

Inventors:

Jaroslav Hynecek - Allen TX

Assignee:

Isetex. Inc - Allen TX

International Classification:

H01L 27148

US Classification:

257223, 257229, 257230, 257234, 257236, 257238, 257242

Abstract:

In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

US Patent:

6608337, Aug 19, 2003

Filed:

Apr 12, 2001

Appl. No.:

09/833194

Inventors:

Jaroslav Hynecek - Allen TX

Assignee:

ISE TEX, Inc - Allen TX

International Classification:

H01L 31113

US Classification:

257290, 257230, 257233, 257258, 257291, 257292

Abstract:

Image sensors with an enhanced QE and MTF in the NIR spectral region are fabricated on the standard substrates. This is achieved by replacing the p+ type doped layer, typically present under the thick field oxide in the inactive regions of the sensor, with an n+ type doped layer. The n+ type layer, which is biased at the Vdd potential, surrounds the entire image sensor array as a guard ring and is separated from the CCD or CMOS array pixels by a suitable potential barrier. The potential barrier prevents collected charge from escaping into the n+ layer regions. Additional embodiments include output diode and MOS transistor designs that use field plates for creating potential barriers that separate these devices from the n+ type doped field regions.

US Patent:

6680222, Jan 20, 2004

Filed:

Feb 8, 2002

Appl. No.:

10/071337

Inventors:

Jaroslav Hynecek - Allen TX

Assignee:

Isetex, Inc - Allen TX

International Classification:

H01L 21339

US Classification:

438144, 438 60, 438 75, 438 79, 438145

Abstract:

Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

US Patent:

6784412, Aug 31, 2004

Filed:

Aug 12, 2002

Appl. No.:

10/217181

Inventors:

Jaroslav Hynecek - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2700

US Classification:

2502081, 377 57

Abstract:

The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication register consists of multi-channel sections that are evenly positioned around the periphery of the image sensing area. The individual charge multiplying register sections are coupled together by only 90-degree multi-channel turns located at the image area array corners. The device allows for the optical image sensing area center to be located near the chip center and consequently near the mechanical package center with the minimum silicon chip area sacrifice.