James F O'Connor

US Patent:

7251583, Jul 31, 2007

Filed:

Aug 31, 2004

Appl. No.:

10/930390

Inventors:

Sudhir M. Desai - Wappingers Falls NY, US
James A. O'Connor - Ulster Park NY, US
Dean A. St. Pier - Wappingers Falls NY, US
Anne-Marie L. Sweetland - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/00
G06F 17/50

US Classification:

702183, 705 29

Abstract:

Use of parts in products is managed to minimize the use of parts that will reach their end of life prior to the products for which those parts are usable. To manage use of a part, end of life data for the part is estimated and compared to the actual or projected end of life data of a product for which the part is to be used or is used. If the comparison indicates that the part will reach its end of life prior to the product, then various factors are considered to determine whether the part is to be used in the product. The factors include cost, scheduling, alternate part availability, redesign options and/or other factors.

US Patent:

7788526, Aug 31, 2010

Filed:

Jan 10, 2007

Appl. No.:

11/621634

Inventors:

James A. O'Connor - Ulster Park NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 6, 711114

Abstract:

Systems, methods, and computer program products for enhancing tolerance of data loss in a disk array system have been provided. Systems include a redundant array of independent disks (RAID) storage system including an array of hard disk devices (HDDs) organized in a two dimensional structure of rows and columns of HDDs. The system includes a full stride logically partitioning the rows and columns of HDDs into rows and columns of elements, the full stride including an element from each HDD in the rows and columns of HDDs, each element in the full stride residing on a physically independent HDD. Each element has an element type, wherein a first element type is a data element and a second element type is a checksum element. The system further includes a row checksum element calculated as a checksum of all data elements in a row of the full stride, and a column checksum element calculated as a checksum of all data elements in a column of the full stride, wherein the row checksum element calculation and the column checksum element calculation intersect at a single data element. The system also includes a device adapter for controlling access to the array of HDDs, the device adapter calculating the row checksum element and the column checksum element, the row checksum element and the column checksum element utilized to correct one or more failures in the array of HDDs.

US Patent:

8041989, Oct 18, 2011

Filed:

Jun 28, 2007

Appl. No.:

11/769936

Inventors:

James A. O'Connor - Ulster Park NY, US
Luiz C. Alves - Hopewell Junction NY, US
William J. Clarke - Poughkeepsie NY, US
Timothy J. Dell - Colchester VT, US
Thomas J. Dewkett - Staatsburg NY, US
Kevin C. Gower - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 62, 714 61, 714 622, 714 42

Abstract:

A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.

US Patent:

8041990, Oct 18, 2011

Filed:

Jun 28, 2007

Appl. No.:

11/769929

Inventors:

James A. O'Connor - Ulster Park NY, US
Luis C. Alves - Hopewell Junction NY, US
William J. Clarke - Poughkeepsie NY, US
Timothy J. Dell - Colchester VT, US
Thomas J. Dewkett - Staatsburg NY, US
Kevin C. Gower - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 622, 714 624, 714 25, 714 42, 714 48

Abstract:

A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.

US Patent:

8086783, Dec 27, 2011

Filed:

Feb 23, 2009

Appl. No.:

12/390731

Inventors:

James A. O'Connor - Ulster Park NY, US
Kevin C. Gower - LaGrangeville NY, US
Warren E. Maule - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711 5

Abstract:

A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.

US Patent:

8099570, Jan 17, 2012

Filed:

Feb 22, 2008

Appl. No.:

12/035695

Inventors:

James A. O'Connor - Ulster Park NY, US
Kanwal Bahri - Hopewell Junction NY, US
Daniel J. Henderson - Georgetown TX, US
Warren E. Maule - Cedar Park TX, US
Michael Mueller - Leonberg, DE
Naresh Nayar - Rochester MN, US
Richard Nicholas - Round Rock TX, US
Eric E. Retter - Austin TX, US
William J. Starke - Round Rock TX, US
Michael R. Trombley - Cary NC, US
Kenneth L. Wright - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711162, 711E12001

Abstract:

Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.

US Patent:

20040078325, Apr 22, 2004

Filed:

Oct 21, 2002

Appl. No.:

10/274622

Inventors:

James O'Connor - Ulster Park NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/60

US Classification:

705/039000

Abstract:

Activation and deactivation of transaction accounts are managed to enable temporary use of those accounts. A transaction account is activated to enable use of the account. In response to activation, the account is temporarily available for a defined window. Upon expiration of the window, the transaction account is deactivated.

US Patent:

20060047587, Mar 2, 2006

Filed:

Aug 31, 2004

Appl. No.:

10/930391

Inventors:

Sudhir Desai - Wappingers Falls NY, US
Denise Frey - Rochester MN, US
James O'Connor - Ulster Park NY, US
Theodore Purvin - Kingston NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
A01K 5/02

US Classification:

705029000

Abstract:

A list of products is created that includes one or more products to be introduced within a future time interval and for zero or more products to be withdrawn within a future time interval, an indication of a withdrawal time. For multiple products of the list of products, a list of parts used by those products is generated. From that list of parts, information is obtained to manage parts of products. This information includes an indication of those parts that are unique, and thus, may be replaced by common parts.