James Mathew

US Patent:

8034706, Oct 11, 2011

Filed:

May 26, 2010

Appl. No.:

12/787684

Inventors:

James Mathew - Boise ID, US
H. Montgomery Manning - Eagle ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/4763

US Classification:

438622, 438612, 257E21627

Abstract:

The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material.

US Patent:

8377819, Feb 19, 2013

Filed:

Sep 20, 2011

Appl. No.:

13/237126

Inventors:

James Mathew - Boise ID, US
H. Montgomery Manning - Eagle ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/4763

US Classification:

438622

Abstract:

The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material.

US Patent:

8461016, Jun 11, 2013

Filed:

Oct 7, 2011

Appl. No.:

13/268066

Inventors:

James Mathew - Boise ID, US
Brett D. Lowe - Boise ID, US
Yunjun Ho - Boise ID, US
H. Jim Fulford - Meridian ID, US
Jie Sun - Boise ID, US
Zhaoli Sun - Lehi UT, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/76

US Classification:

438427, 438435, 438436, 257E21548

Abstract:

A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500 C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800 C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

US Patent:

8569130, Oct 29, 2013

Filed:

Jul 28, 2011

Appl. No.:

13/192763

Inventors:

James Mathew - Boise ID, US
Gordon Haller - Boise ID, US
Ronald A. Weimer - Boise ID, US
John Hopkins - Boise ID, US
Vinayak K. Shamanna - Boise ID, US
Sanjeev Sapra - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/336

US Classification:

438257, 438211, 257E21209, 257E21613, 257314

Abstract:

Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.

US Patent:

20030087514, May 8, 2003

Filed:

Nov 2, 2001

Appl. No.:

10/007929

Inventors:

Sanh Tang - Boise ID, US
James Mathew - Boise ID, US

International Classification:

H01L021/4763

US Classification:

438/630000

Abstract:

A method used to form a semiconductor device comprises patterning a hard mask layer with a first pattern, then only partially etching through an underlying dielectric layer using the hard mask as a pattern. Next, the hard mask is patterned with a second pattern and the dielectric layer is completely etched through using the hard mask as a pattern. The dielectric etch stops on an etch stop layer. Finally, the etch stop layer is patterned which is defined only by the first pattern of the hard mask.

US Patent:

20070202677, Aug 30, 2007

Filed:

Feb 27, 2006

Appl. No.:

11/363661

Inventors:

James Mathew - Boise ID, US
H. Manning - Eagle ID, US

International Classification:

H01L 21/44

US Classification:

438597000

Abstract:

The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.

US Patent:

20080246124, Oct 9, 2008

Filed:

Apr 4, 2007

Appl. No.:

11/696262

Inventors:

James Mathew - Boise ID, US
Prashant Raghu - Boise ID, US
Jaydeb Goswami - Boise ID, US

International Classification:

H01L 21/302
H01L 23/58

US Classification:

257632, 438710, 257E23001, 257E21214

Abstract:

A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening.

US Patent:

20090176365, Jul 9, 2009

Filed:

Mar 11, 2009

Appl. No.:

12/401996

Inventors:

James Mathew - Boise ID, US
H. Montgomery Manning - Eagle ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/768

US Classification:

438622, 257E21585

Abstract:

The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.