James Thomas Hanna

Author:

James P. Hanna

ISBN #:

0792397991

Author:

James Hanna

ISBN #:

0835902056

Author:

James Hanna

ISBN #:

0960702431

Author:

James Milton Hanna

ISBN #:

1930052073

Author:

James Milton Hanna

ISBN #:

1930052154

Author:

James Milton Hanna

ISBN #:

1930052227

Author:

James A. Hanna

ISBN #:

0919100724

Author:

James A. Hanna

ISBN #:

0919822703

US Patent:

8199695, Jun 12, 2012

Filed:

Apr 10, 2007

Appl. No.:

11/733432

Inventors:

Daniel N. de Araujo - Cedar Park TX, US
James T. Hanna - College Station TX, US
James O. Nicholson - Pflugerville TX, US
Bruce J. Wilkie - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 1/7073

US Classification:

370324, 370503, 370511, 370520, 709248

Abstract:

Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

US Patent:

20070260545, Nov 8, 2007

Filed:

May 2, 2006

Appl. No.:

11/381237

Inventors:

Steven Bade - Georgetown TX, US
Richard Dayan - Wake Forest NC, US
James Hanna - Austin TX, US
Andrew Kegel - Redmond WA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 9/00
G06F 12/14
H04L 9/32
G06F 11/30
H04K 1/00

US Classification:

705051000, 713193000, 713194000, 713164000

Abstract:

Embodiments of the present invention address deficiencies of the art in respect to trusted platform module (TPM) unification in a trusted computing environment and provide a novel and non-obvious method, system and computer program product for trusted platform module data harmonization. In one embodiment of the invention, a TPM log harmonization method can include designating both a single master TPM for a master node among multiple nodes, and also a multiplicity of subsidiary TPMs for remaining ones of the nodes. The method further can include extending the single master TPM with a measurement representing a rendezvous operation for the nodes.

US Patent:

20120203933, Aug 9, 2012

Filed:

Apr 17, 2012

Appl. No.:

13/448785

Inventors:

Daniel N. de Araujo - Cedar Park TX, US
James T. Hanna - College Station TX, US
James O. Nicholson - Pflugerville TX, US
Bruce J. Wilkie - Georgetown TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 1/12
G06F 15/16

US Classification:

709248

Abstract:

Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

US Patent:

50863878, Feb 4, 1992

Filed:

May 27, 1988

Appl. No.:

7/203586

Inventors:

Ronald X. Arroyo - Elgin TX
James T. Hanna - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 104

US Classification:

395550

Abstract:

A clocking circuit connected to a processor for regulating processor operation and including a control circuit that produces a clock signal at a first frequency or for producing a clock signal at a designated one of a plurality of other selectable frequencies in response to a change signal from the processor. The control circuit is connected to a designating circuit that provides a signal to the control circuit to designate one of the selectable frequencies. In the preferred embodiment, the clocking circuit includes a register addressable by the processor and a frequency generator that generates several signals having unique frequencies. The processor may designate one of the frequencies as the clocking frequency by providing the appropriate data to the register. Upon the occurrence of an external event such as a DMA request or an interrupt, the control circuit will provide the clocking signal at a predetermined frequency.

US Patent:

49071505, Mar 6, 1990

Filed:

Jul 26, 1988

Appl. No.:

7/225570

Inventors:

Ronald X. Arroyo - Elgin TX
Michael N. Day - Austin TX
Jimmie D. Edrington - Georgetown TX
James T. Hanna - Austin TX
Gary T. Hunt - Austin TX
Steven T. Pancoast - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1130
G06F 1216

US Classification:

364200

Abstract:

A method and apparatus for powering down a computer system while saving the state of the system at power down is disclosed. The system maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at that same point at a later time. The time at which the system may be powered down and then powered back up again is totally arbitrary and depends only upon the user of the system. At the time the system is powered off, the contents of all active registers as well as the states of all I/O devices in the system are stored in a special save area of system memory. This special save area is provided with power during the suspended time in order to retain the state of the system at the time it was powered down. By using this special save suspend area, the main memory area of the system is available to any application programs independently of the system save memory requirements. Additionally, the system may be powered on and off under software control thereby providing the capability for unattended system operation using an alarm function.