James Miller Derderian

US Patent:

6869828, Mar 22, 2005

Filed:

May 27, 2003

Appl. No.:

10/446382

Inventors:

James M. Derderian - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L021/44

US Classification:

438109, 438118, 257777, 257784

Abstract:

A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device over the first semiconductor device and a portion of at least one discrete conductive element protruding thereabove. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate.

US Patent:

6870269, Mar 22, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/132903

Inventors:

James M. Derderian - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L023/48

US Classification:

257777, 257686, 257784

Abstract:

A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device over the first semiconductor device and a portion of at least one discrete conductive element protruding thereabove. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate.

US Patent:

6940181, Sep 6, 2005

Filed:

Oct 21, 2003

Appl. No.:

10/690339

Inventors:

James M. Derderian - Boise ID, US
Nathan R. Draney - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L023/28

US Classification:

257787, 257753, 438459, 438460, 438690, 438691, 216 11, 216 48

Abstract:

A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over, a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin layer or film of reinforcement material fills grooves, fractures and scratches in the back side of the wafer, enhance the rigidity of the wafer and provide a planar, smooth, back side surface layer. The reinforcement material counteracts internal stresses of the wafer tending to warp, crack and propagate lattice defects in the wafer. The reinforcement material may also be configured to act as a die attach adhesive, may provide an ionic barrier, and may remain as part of the packaging for semiconductor dice singulated from the wafer.

US Patent:

7056812, Jun 6, 2006

Filed:

Nov 4, 2004

Appl. No.:

10/981073

Inventors:

James M. Derderian - Boise ID, US
Nathan R. Draney - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/30

US Classification:

438459, 435690, 435691, 216 11, 216 48

Abstract:

A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin layer or film of reinforcement material fills grooves, fractures and scratches in the back side of the wafer, enhance the rigidity of the wafer and provide a planar, smooth, back side surface layer. The reinforcement material counteracts internal stresses of the wafer tending to warp, crack and propagate lattice defects in the wafer. The reinforcement material may also be configured to act as a die attach adhesive, may provide an ionic barrier, and may remain as part of the packaging for semiconductor dice singulated from the wafer.

US Patent:

7064069, Jun 20, 2006

Filed:

Oct 21, 2003

Appl. No.:

10/690174

Inventors:

Nathan R. Draney - Boise ID, US
James M. Derderian - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438690, 438734, 438737, 438750

Abstract:

A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with the wafer material by one or more suitable thinning or planarization techniques. The planarization material may be applied as a thin layer or film of a hardenable material to the rough, bare back side of a wafer to produce a planar surface when hardened. The planarization material is selected to exhibit a material removal rate approximating the removal rate of the wafer material for a given removal technique such as etching, mechanical abrasion or chemical-mechanical planarization (CMP). This approach to wafer thinning and planarization results in improved process control in the form of uniform material removal rates, reduction in wafer warpage, final surface smoothness and planarity, and even distribution of residual stresses.

US Patent:

7276393, Oct 2, 2007

Filed:

Aug 26, 2004

Appl. No.:

10/927550

Inventors:

James M. Derderian - Boise ID, US
Bret K. Street - Meridian ID, US
Eric T. Mueller - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/00

US Classification:

438 51, 438 48, 438 55, 438 64, 257433, 257724, 257E21499

Abstract:

Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

US Patent:

7332372, Feb 19, 2008

Filed:

Feb 2, 2004

Appl. No.:

10/770890

Inventors:

James M. Derderian - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44
H01L 23/02
H01L 23/52
H01L 23/48
H01L 27/146

US Classification:

438109, 438107, 438118, 257686, 257777, 257782, 257783, 257784, 257E27137, 257E27144, 257E27161

Abstract:

A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device over the first semiconductor device and a portion of at least one discrete conductive element protruding thereabove. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate.

US Patent:

7335533, Feb 26, 2008

Filed:

Nov 12, 2004

Appl. No.:

10/987714

Inventors:

James M. Derderian - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44
H01L 21/46
H01L 23/02
H01L 23/52
H01L 23/48
H01L 29/40
H01L 27/146
H01L 27/148

US Classification:

438109, 438107, 438118, 438455, 257686, 257777, 257782, 257783, 257784, 257E27137, 257E27144, 257E27161

Abstract:

A method for assembling semiconductor devices includes providing a first semiconductor device, applying a predetermined volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device adjacent to the first semiconductor device in superimposed relation thereto. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing or hardening, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate.