James E Cortney

US Patent:

54189217, May 23, 1995

Filed:

May 5, 1992

Appl. No.:

7/878810

Inventors:

James E. Cortney - San Jose CA
Jaishankar M. Menon - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1200
G06F 1208

US Classification:

395425

Abstract:

A method and means using a fast write in order to eliminate DASD time from the write response time as seen by the host; eliminate some DASD writes due to overwrites caused by later host writes to previously updated blocks in cache; and reduce DASD seeks because destages will be postponed until many destages can be done to a track or cylinder. This is effectuated by destaging from the cache only the least recently referenced original or updated block and all other original or updated blocks occupying the same logical track and ordered in a predefined lower LRU range, the destage being initiated responsive to a cache miss. The destaging step is selectable from a set of destaging steps varying in their robustness.