Jaidev P Patwardhan

US Patent:

8352685, Jan 8, 2013

Filed:

Aug 20, 2010

Appl. No.:

12/860505

Inventors:

Peter J. Bannon - Concord MA, US
Andrew J. Beaumont-Smith - Cambridge MA, US
Ramesh Gunna - San Jose CA, US
Wei-han Lien - San Jose CA, US
Brian P. Lilly - San Francisco CA, US
Jaidev P. Patwardhan - Sunnyvale CA, US
Shih-Chieh R. Wen - San Jose CA, US
Tse-Yu Yeh - Cupertino CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711135, 711118

Abstract:

In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed. ” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

US Patent:

8566528, Oct 22, 2013

Filed:

Dec 10, 2012

Appl. No.:

13/709649

Inventors:

Andrew J. Beaumont-Smith - Cambridge MA, US
Ramesh B. Gunna - San Jose CA, US
Wei-han Lien - San Jose CA, US
Brian P. Lilly - San Francisco CA, US
Jaidev P. Patwardhan - Sunnyvale CA, US
Shih-Chieh R. Wen - San Jose CA, US
Tse-Yu Yeh - Cupertino CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711135, 711118

Abstract:

In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed. ” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

US Patent:

20090249045, Oct 1, 2009

Filed:

Mar 31, 2008

Appl. No.:

12/060204

Inventors:

Thomas Benjamin BERG - Portland OR, US
Ryan C. KINTER - Seattle WA, US
Jaidev Prasad PATWARDHAN - Sunnyvale CA, US
Radhika THEKKATH - Palo Alto CA, US

Assignee:

MIPS TECHNOLOGIES, INC. - Mountain View CA

International Classification:

G06F 9/30

US Classification:

712227, 712E09016

Abstract:

A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.

US Patent:

20090249046, Oct 1, 2009

Filed:

Mar 31, 2008

Appl. No.:

12/060214

Inventors:

Thomas Benjamin BERG - Portland OR, US
Ryan C. KINTER - Seattle WA, US
Jaidev Prasad PATWARDHAN - Sunnyvale CA, US
Radhika THEKKATH - Palo Alto CA, US

Assignee:

MIPS TECHNOLOGIES, INC. - Mountain View CA

International Classification:

G06F 9/30

US Classification:

712227, 712E09032

Abstract:

A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.

US Patent:

20130067284, Mar 14, 2013

Filed:

Sep 10, 2012

Appl. No.:

13/609047

Inventors:

Thomas Benjamin Berg - Portland OR, US
Ryan C. Kinter - Seattle WA, US
Jaidev Prasad Patwardhan - Sunnyvale CA, US
Radhika Thekkath - Palo Alto CA, US

Assignee:

MIPS TECHNOLOGIES, INC. - Sunnyvale CA

International Classification:

G06F 11/26

US Classification:

714 37, 714E11159

Abstract:

A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.

US Patent:

20230067109, Mar 2, 2023

Filed:

Aug 23, 2022

Appl. No.:

17/893913

Inventors:

- Cupertino CA, US
John G. DORSEY - San Francisco CA, US
Ronit BANERJEE - Cupertino CA, US
Kushal DALMIA - Santa Clara CA, US
Daniel A. CHIMENE - San Francisco CA, US
Jaidev P. PATWARDHAN - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 15/78
G06F 11/34
G06F 9/48

Abstract:

Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

US Patent:

20230040310, Feb 9, 2023

Filed:

Aug 3, 2021

Appl. No.:

17/392929

Inventors:

- Cupertino CA, US
Bryan R. HINCH - Campbell CA, US
Ronit BANERJEE - Cupertino CA, US
Kushal DALMIA - Santa Clara CA, US
Daniel A. CHIMENE - San Francisco CA, US
Jaidev P. PATWARDHAN - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 9/50

Abstract:

Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics of the first thread can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.