Jad B Rizk

US Patent:

20130257523, Oct 3, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/436382

Inventors:

Cho-Ying Lu - Hillsboro OR, US
Chun Lee - Portland OR, US
Jad B. Rizk - Portland OR, US

International Classification:

G05F 1/10

US Classification:

327536

Abstract:

Embodiments of a calibration circuit for a current source which may include a first control switch, a second control switch, and a capacitor. In embodiments, the first control switch may be operable to couple the capacitor to the current source and the second control switch may be operable to couple the capacitor to a reference current source to enable the capacitor to be charged or discharged according to a first control signal provided to the first control switch and a second control signal provided to the second control switch. In embodiments, the calibration circuit may be included in a digital-to-analog (DAC) converter.

US Patent:

20140008732, Jan 9, 2014

Filed:

Nov 14, 2011

Appl. No.:

13/976081

Inventors:

Sami Hyvonen - Beaverton OR, US
Jad B. Rizk - Portland OR, US
Frank O'Mahony - Portland OR, US

International Classification:

H01L 27/088

US Classification:

257390

Abstract:

Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.

US Patent:

20220239222, Jul 28, 2022

Filed:

Apr 6, 2022

Appl. No.:

17/714969

Inventors:

- Santa Clara CA, US
Fabrice Paillet - Portland OR, US
Rinkle Jain - Portland OR, US
Jad Rizk - Portland OR, US
Danny Bronstein - Haifa, IL
Ahmad Arnaot - Acre, IL

International Classification:

H02M 3/07
H02M 1/00
G06F 1/3234
H03K 5/24

Abstract:

An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

US Patent:

20210075316, Mar 11, 2021

Filed:

Sep 6, 2019

Appl. No.:

16/563495

Inventors:

- Santa Clara CA, US
Fabrice Paillet - Portland OR, US
Rinkle Jain - Portland OR, US
Jad Rizk - Portland OR, US
Danny Bronstein - Haifa, IL
Ahmad Arnaot - Acre, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02M 3/07
H02M 1/00
H03K 5/24
G06F 1/3234

Abstract:

An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

US Patent:

20170148791, May 25, 2017

Filed:

Feb 6, 2017

Appl. No.:

15/425393

Inventors:

- Santa Clara CA, US
JAD B. RIZK - Portland OR, US
FRANK O'MAHONY - Portland OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 27/088
H01L 29/93
H01L 29/78
H01L 27/12
H01L 29/423

Abstract:

Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.

US Patent:

20140197916, Jul 17, 2014

Filed:

Dec 29, 2011

Appl. No.:

13/976080

Inventors:

Jad B. Rizk - Portland OR, US

International Classification:

H01F 27/28
H01F 41/04

US Classification:

336200, 296021

Abstract:

Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design thereof. In some cases, a metal dummy schema may be disposed in a layer proximate an upper surface of the inductor. The techniques may be implemented to improve overall inductor performance while enabling area scaling effects such as shrinking of inductor-to-inductor spacing on a die and/or increasing the quantity of inductors that may be manufactured on a die. In some cases, conductive metal dummies may be disposed in a region of minimal or non-peak magnetic field relative to the inductor, orthogonal to current flow in the inductor, and/or so as to minimize their occupation of the overall area of the inductor. The techniques may be implemented in analog circuits such as inductor-capacitor phase-locked loops (LC-PLLs), high-volume architectures, processor microarchitectures, applications involving stringent jitter requirements, microprocessor clocking, and wireless communication systems.