William T Motsiff

US Patent:

6335229, Jan 1, 2002

Filed:

Oct 13, 1999

Appl. No.:

09/417289

Inventors:

Wilbur D. Pricer - Charlotte VT
Rosemary A. Previti-Kelly - Burlington VT
William T. Motsiff - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2182

US Classification:

438132, 257529

Abstract:

A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

US Patent:

6340630, Jan 22, 2002

Filed:

Mar 28, 2000

Appl. No.:

09/536557

Inventors:

Daniel George Berger - Wappingers Falls NY
Guy Paul Brouillette - Daudelin, CA
David Hirsch Danovitch - Des Aigles, CA
Peter Alfred Gruber - Mohegan Lake NY
Bruce Lee Humphrey - Jericho VT
Michael Liehr - Yorktown Heights NY
William Thomas Motsiff - Essex Junction VT
Carlos Juan Sambucetti - Croton-on-Hudson NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

A01L 2144

US Classification:

438613, 438612, 438614, 438616

Abstract:

A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip. The aligned mold/wafer assembly is then passed through a reflow furnace to effect the transfer of the low melting temperature solder in the mold cavities onto the tip of the high melting temperature solder bumps on the wafer. A dual metallurgical composition bump is thereby formed by the two different solder alloys.

US Patent:

6375159, Apr 23, 2002

Filed:

Apr 30, 1999

Appl. No.:

09/302915

Inventors:

Timothy H. Daubenspeck - Colchester VT
William T. Motsiff - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

251529, 257762, 257764

Abstract:

A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy. Fabrication methods for providing overlaying material to the entire fuse link line, or to selective portions of the fuse link line are presented.

US Patent:

6420772, Jul 16, 2002

Filed:

Oct 13, 1999

Appl. No.:

09/417438

Inventors:

Kurt R. Kimmel - Jericho VT
J. Alex Chediak - Wappingers Falls NY
William T. Motsiff - Essex Junction VT
Wilbur D. Pricer - Charlotte VT
Richard Q. Williams - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

257529

Abstract:

A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable. The magnetic device can be programmed into one of three magnetic field orentations or states. Conventional VLSI fabrication steps are used for compatability with low-k dielectric Back-End-Of-Line (BEOL) processing.

US Patent:

6426557, Jul 30, 2002

Filed:

Feb 25, 2000

Appl. No.:

09/512952

Inventors:

Timothy Daubenspeck - Colchester VT
Stephen E. Luce - Underhill VT
William Motsiff - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2940

US Classification:

257750, 257774, 257760, 257761

Abstract:

A controlled collapse chip connection (C4) structure having stronger resistance to failure is constructed for use with integrated circuit devices having copper wiring. Failure resistance is obtained by replacing the mechanically weak final passivation to copper interface. The weak interface is eliminated by use of a specific peg on peg structure together with a layer of shunt metal having excellent adhesion and barrier characteristics. A shunt metal, e. g. , Ta or TaN, is placed between both the copper and final passivation and the copper and C4 metals such that it overlaps the edge of the peg defined wiring mesh to encase the copper. Overlap is obtained by the peg on peg structure where a SiO peg defines the copper wire mesh and a smaller Si N peg placed on the SiO peg defines the overlap above the mesh wire and provides the ability to pattern the overlayer shunt without exposure of the copper conductor.

US Patent:

6440834, Aug 27, 2002

Filed:

Apr 6, 2001

Appl. No.:

09/827871

Inventors:

Timothy Harrison Daubenspeck - Colchester VT
William Thomas Motsiff - Essex Junction VT
Jed Hickory Rankin - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438601, 438132, 438600, 257529

Abstract:

A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.

US Patent:

6455914, Sep 24, 2002

Filed:

Apr 26, 2001

Appl. No.:

09/842545

Inventors:

Dennis P. Bouldin - Essex Junction VT
Timothy H. Daubenspeck - Colchester VT
William T. Motsiff - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

257529, 257536, 257537, 257752, 257762

Abstract:

A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of âeasy to laser deleteâ thin metal fuses within segments of thick metal lines.

US Patent:

6458630, Oct 1, 2002

Filed:

Oct 14, 1999

Appl. No.:

09/417853

Inventors:

Timothy H. Daubenspeck - Colchester VT
William A. Klaasen - Underhill VT
William T. Motsiff - Essex Junction VT
Rosemary A. Previti-Kelly - Burlington VT
Jed H. Rankin - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2128

US Classification:

438131, 438600, 438610, 438781

Abstract:

A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.