Hyong Y Lee

US Patent:

20110297329, Dec 8, 2011

Filed:

Oct 5, 2010

Appl. No.:

12/898623

Inventors:

Steve Canale - Simi Valley CA, US
David J. Zapp - Simi Valley CA, US
Daniel E. Sanchez - Camarillo CA, US
Hung V. Phan - Simi Valley CA, US
Hyong Y. Lee - Thousand Oaks CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 21/687

US Classification:

156756, 156761

Abstract:

Disclosed are systems, devices and methodologies for debonding wafers from carrier plates. In certain wafer processing operations, it is desirable to temporarily mount a wafer on a carrier plate for support and ease of handling. Such a mounting can be achieved by bonding the wafer and the carrier plate with an adhesive. Once such operations are completed, the wafer needs to be debonded from the carrier plate. Such a debonding process can be achieved by applying a suction force to the wafer-carrier plate assembly. Various debonding systems, devices and methodologies, and related features, are disclosed.

US Patent:

55942628, Jan 14, 1997

Filed:

Apr 7, 1995

Appl. No.:

8/418747

Inventors:

Hyong Y. Lee - Beavercreek OH
Belinda Johnson - Dayton OH
Rocky Reston - Beavercreek OH
Chris Ito - Colorado Springs CO
Gerald Trombley - Centerville OH
Charles Havasy - Beavercreek OH

Assignee:

The United States of America as represented by the Secretary of the Air
Force - Washington DC

International Classification:

H01L 310256
H01L 2920

US Classification:

257192

Abstract:

The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al. sub. x Ga. sub. 1-x As 0. 2. ltoreq. x. ltoreq. 1 barrier layer. At temperatures greater than 250. degree. C. , the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350. degree. C. ambient temperature.

US Patent:

54119022, May 2, 1995

Filed:

Jun 6, 1994

Appl. No.:

8/254722

Inventors:

Hyong Y. Lee - Fairborn OH
Belinda Johnson - Dayton OH
Rocky Reston - Beavercreek OH
Chris Ito - Colorado Springs CO
Gerald Trombley - Centerville OH
Charles Havasy - Beavercreek OH

Assignee:

The United States of America as represented by the Secretary of the Air
Force - Washington DC

International Classification:

H01L 21338

US Classification:

437 40

Abstract:

The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al. sub. x Ga. sub. 1-x As (0. 2. ltoreq. x. ltoreq. 1) barrier layer. At temperatures greater than 250. degree. C. , the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350. degree. C. ambient temperature.

US Patent:

20170125275, May 4, 2017

Filed:

Jan 9, 2017

Appl. No.:

15/401344

Inventors:

- Woburn MA, US
Daniel Kwadwo Amponsah Berkoh - West Hills CA, US
David James Zapp - Deceased, US
Steve Canale - Simi Valley CA, US
Hyong Yong Lee - Thousand Oaks CA, US
Daniel Eduardo Sanchez - Camarillo CA, US
Hung V. Phan - Simi Valley CA, US

International Classification:

H01L 21/683
B32B 43/00

Abstract:

Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

US Patent:

20160167359, Jun 16, 2016

Filed:

Feb 19, 2016

Appl. No.:

15/048661

Inventors:

- Woburn MA, US
David J. Zapp - , US
Daniel Eduardo Sanchez - Camarillo CA, US
Hung V. Phan - Simi Valley CA, US
Hyong Yong Lee - Thousand Oaks CA, US

International Classification:

B32B 43/00
H01L 21/683

Abstract:

A first surface of a debonder defines a recess to hold an assembly that includes a wafer bonded to a carrier plate having a first diameter that is larger than a second diameter of the wafer. The carrier plate includes a peripheral area not covered by the wafer, and when the wafer of the assembly is placed within the recess, a portion of the peripheral area of the carrier plate engages a portion of the first surface. A second surface of the debonder is disposed in the recess and is separated from the first surface, where the second surface includes suction openings that deliver a suction force to the recess, and a portion of the second surface is in contact with a heat source.

US Patent:

20160167360, Jun 16, 2016

Filed:

Feb 19, 2016

Appl. No.:

15/048673

Inventors:

- Woburn MA, US
David J. Zapp - , US
Daniel Eduardo Sanchez - Camarillo CA, US
Hung V. Phan - Simi Valley CA, US
Hyong Yong Lee - Thousand Oaks CA, US

International Classification:

B32B 43/00
H01L 21/67
H01L 21/683

Abstract:

A first surface of a debonder defines a recess that holds an assembly that includes a wafer bonded to a carrier plate having a first diameter that is larger than a second diameter of the wafer. The plate includes a peripheral area not covered by the wafer, and when the wafer of the assembly is placed within the recess, a portion of the peripheral area of the plate engages a portion of the first surface. A second surface of the debonder is disposed in the recess and is separated from the first surface. The second surface includes suction openings that deliver suction to the recess. A third surface of the debonder substantially connects the first and the second surfaces and includes an opening dimensioned to limit a pressure differential between the recess and outside the recess during application of the suction.

US Patent:

20140262053, Sep 18, 2014

Filed:

May 27, 2014

Appl. No.:

14/287660

Inventors:

- Woburn MA, US
David J. Zapp - Simi Valley CA, US
Daniel Eduardo Sanchez - Camarillo CA, US
Hung V. Phan - Simi Valley CA, US
Hyong Yong Lee - Thousand Oaks CA, US

Assignee:

Skyworks Solutions, Inc. - Woburn MA

International Classification:

B32B 43/00
H01L 21/67

US Classification:

156707, 156758

Abstract:

Disclosed are systems, devices and methodologies for debonding wafers from carrier plates. In certain wafer processing operations, it is desirable to temporarily mount a wafer on a carrier plate for support and ease of handling. Such a mounting can be achieved by bonding the wafer and the carrier plate with an adhesive. Once such operations are completed, the wafer needs to be debonded from the carrier plate. Such a debonding process can be achieved by applying a suction force to the wafer-carrier plate assembly. Various debonding systems, devices and methodologies, and related features, are disclosed.