Hung Dat Lai

US Patent:

49690299, Nov 6, 1990

Filed:

Apr 27, 1987

Appl. No.:

7/047551

Inventors:

Hisashige Ando - Santa Clara CA
Hung C. Lai - Cupertino CA
John J. Zasio - Sunnyvale CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H01L 2710
H01L 2702

US Classification:

357 45

Abstract:

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurlity of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells.

US Patent:

50953567, Mar 10, 1992

Filed:

Oct 9, 1990

Appl. No.:

7/594309

Inventors:

Hisashige Ando - Santa Clara CA
Hung C. Lai - Cupertino CA
John J. Zasio - Sunnyvale CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H01L 2710
H01L 2702

US Classification:

357 45

Abstract:

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurality of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells.

US Patent:

42258499, Sep 30, 1980

Filed:

May 1, 1978

Appl. No.:

5/901412

Inventors:

Hung C. Lai - Cupertino CA

Assignee:

Fujitsu Limited

International Classification:

G06F 704

US Classification:

3401462

Abstract:

An N-bit magnitude comparator of tree design having a plurality of one-bit magnitude comparators connected to a cascading network with a first stage adapted to receive signals from each pair of the one-bit magnitude comparators and subsequent stages for receiving signals from the preceding stage in the cascade network. The first and every alternate stage thereafter in the cascading circuit comprises means for inverting the signal polarity to the input of that stage so as to achieve one gate delay per circuit.