Hongning H Yang from Laveen, AZ, age 69

Us Patents

Semiconductor Devices And Method Of Fabrication
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US Patent:

7393752, Jul 1, 2008
Filed:

Jul 25, 2005
Appl. No.:

11/189587
Inventors:

Hongning Yang - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/336
US Classification:

438302, 438525, 438527
Abstract:

A semiconductor having an 5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (

Composite Capacitor And Method For Forming The Same
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US Patent:

7411270, Aug 12, 2008
Filed:

Apr 3, 2006
Appl. No.:

11/397493
Inventors:

Won Gi Min - Chandler AZ, US
Geno L. Fallico - Cedar Park TX, US
Amanda M. Kroll - Plfugerville TX, US
Hongning Yang - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 27/04
US Classification:

257532, 257499, 257528, 257E27048, 438381, 438393
Abstract:

An electronic assembly () includes a substrate (), a capacitor having first and second conductors () formed over the substrate, a first set of conductive members () formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members () formed over the substrate and being electrically connected to the second conductor of the capacitor.

Dual Gate Ldmos Device Fabrication Methods
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US Patent:

7608513, Oct 27, 2009
Filed:

Jan 25, 2007
Appl. No.:

11/626928
Inventors:

Hongning Yang - Chandler AZ, US
Veronique C. Macary - Chandler AZ, US
Won Gi Min - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/336
US Classification:

438286, 257E21427
Abstract:

An N-channel device () is described having a lightly doped substrate (′) in which adjacent or spaced-apart P (′) and N () wells are provided. A lateral isolation wall () surrounds at least a portion of the substrate (′) and is spaced apart from the wells (). A first gate (G) () overlies the P () well or the substrate (′) between the wells () or partly both. A second gate (G) (), spaced apart from G (), overlies the N-well (). A body contact () to the substrate (′) is spaced apart from the isolation wall () by a first distance () within the space charge region of the substrate (′) to isolation wall () PN junction. When the body contact () is connected to G (), a predetermined static bias Vg is provided to G () depending upon the isolation wall bias (Vbias) and the first distance (). The resulting device () operates at higher voltage with lower Rdson and less HCI.

Semiconductor Devices
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US Patent:

7649234, Jan 19, 2010
Filed:

May 30, 2008
Appl. No.:

12/129861
Inventors:

Hongning Yang - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/336
US Classification:

257408, 438525, 438527
Abstract:

An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain.

Methods For Forming Cascode Current Mirrors
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US Patent:

7700417, Apr 20, 2010
Filed:

Mar 15, 2007
Appl. No.:

11/686439
Inventors:

Hongning Yang - Chandler AZ, US
Geoffrey W. Perkins - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/00
US Classification:

438149, 438154, 438292, 438301, 438510, 438514, 438981, 257E21533, 257E21675
Abstract:

A cascode amplifier (CA) () is described having a bottom transistor (T) with a relatively thin gate dielectric () and higher ratio (RB) of channel length (Lch) to width (W) and a series coupled top transistor (T) with a relatively thick gate dielectric () and a lower ratio (RT) of channel length (Lch) to width (W). An improved cascode current mirror (CCM) () is formed using a coupled pair of CAs (′), one () forming the reference current (RC) side () and the other (′) forming the mirror current side () of the CCM (). The gates (′) of the bottom transistors (T, T) are tied together and to the common node () between the series coupled bottom (T) and top (T) transistors of the RC side (), and the gates (′) of the top transistors (T, T) are coupled together and to the top drain node () of the RC side (). The area of the CCM () can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.

Ldmos Device And Method
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US Patent:

7776700, Aug 17, 2010
Filed:

Jan 4, 2007
Appl. No.:

11/650188
Inventors:

Hongning Yang - Chandler AZ, US
Veronique C. Macary - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/336
US Classification:

438286, 257408, 257549
Abstract:

An N-channel device () is described having a very lightly doped substrate () in which spaced-apart P () and N () wells are provided, whose lateral edges () extending to the surface (). The gate () overlies the surface () between the P () and N () wells. The P-well edge () adjacent the source () is substantially aligned with the left gate edge (). The N-well edge () lies at or within the right gate edge (), which is spaced a first distance () from the drain (). The N-well () desirably includes a heavier doped region () in ohmic contact with the drain () and with its left edge () located about half way between the right gate edge () and the drain (). A HALO implant pocket () is provided underlying the left gate edge () using the gate () as a mask. The resulting device () operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.

Dual Gate Ldmos Devices
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US Patent:

7795674, Sep 14, 2010
Filed:

Sep 16, 2009
Appl. No.:

12/560588
Inventors:

Hongning Yang - Chandler AZ, US
Veronique C. Macary - Chandler AZ, US
Won Gi Min - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 29/78
US Classification:

257336, 257E29256
Abstract:

An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Cascode Current Mirror And Method
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US Patent:

7851834, Dec 14, 2010
Filed:

Mar 2, 2010
Appl. No.:

12/715941
Inventors:

Hongning Yang - Chandler AZ, US
Geoffrey W. Perkins - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 29/94
US Classification:

257288, 257341, 257401, 257E29027, 257E21177, 438149
Abstract:

Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.