Hideki Komori

US Patent:

6573140, Jun 3, 2003

Filed:

Mar 16, 2001

Appl. No.:

09/810155

Inventors:

Jusuke Ogura - Cupertino CA
Kiyoshi Izumi - San Jose CA
Masaru Yano - Sunnyvale CA
Hideki Komori - Santa Clara CA
Tuan Pham - Santa Clara CA
Angela Hui - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 218247

US Classification:

438261, 438262, 438634

Abstract:

The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

US Patent:

6713809, Mar 30, 2004

Filed:

Mar 16, 2001

Appl. No.:

09/809969

Inventors:

Jusuke Ogura - Cupertino CA
Kazuhiro Kurihara - Sunnyvale CA
Masaru Yano - Sunnyvale CA
Hideki Komori - Santa Clara CA
Tuan Pham - Santa Clara CA
Angela Hui - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 29788

US Classification:

257315, 257314, 257316, 257317

Abstract:

The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

US Patent:

62182277, Apr 17, 2001

Filed:

Oct 25, 1999

Appl. No.:

9/426239

Inventors:

Steven K. Park - Cupertino CA
Arvind Halliyal - Sunnyvale CA
Hideki Komori - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 218238

US Classification:

438216

Abstract:

A process for fabricating an ONO structure for a MONOS type Flash cell includes growing a first silicon oxide layer over a semiconductor substrate. Thereafter, a silicon nitride layer is formed to overlie the first silicon oxide layer, and a polycrystalline silicon layer is deposited to overlie the silicon nitride layer. By utilizing the polycrystalline silicon layer as the top layer of the ONO structure, a resist layer can be cleaned more aggressively than if the top layer of the ONO structure were an oxide layer. A second silicon oxide layer overlies the polycrystalline layer, of the ONO structure. Since the second silicon oxide layer is deposited on top of polycrystalline silicon after the resist material is cleaned, some resist material can remain on the polycrystalline layer without degrading the performance of the MONOS type cell.

US Patent:

62652680, Jul 24, 2001

Filed:

Oct 25, 1999

Appl. No.:

9/426672

Inventors:

Arvind Halliyal - Sunnyvale CA
Robert B. Ogle - San Jose CA
Hideki Komori - Santa Clara CA
Kenneth Au - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu, Ltd. - Kanagawa

International Classification:

H01L 218247

US Classification:

438261

Abstract:

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800. degree. C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

US Patent:

6117730, Sep 12, 2000

Filed:

Oct 25, 1999

Appl. No.:

9/427402

Inventors:

Hideki Komori - Santa Clara CA
Kenneth Au - Fremont CA
Mark Ramsbey - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 218247

US Classification:

438258

Abstract:

A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

US Patent:

62486284, Jun 19, 2001

Filed:

Oct 25, 1999

Appl. No.:

9/426430

Inventors:

Arvind Halliyal - Sunnyvale CA
David K. Foote - San Jose CA
Hideki Komori - Santa Clara CA
Kenneth W. Au - Fremont CA

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257

Abstract:

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.

US Patent:

62423053, Jun 5, 2001

Filed:

Oct 25, 1999

Appl. No.:

9/427404

Inventors:

David K. Foote - San Jose CA
Hideki Komori - Santa Clara CA
Bharath Rangarajan - Santa Clara CA
Fei Wang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438262

Abstract:

A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure overlying the semiconductor substrate. Thereafter, a hard mask layer is formed to overlie ONO structure, the hard mask layer having an upper surface. To form a trench for the buried bit-line, an etch process is performed on the ONO structure. Thereafter, silicon dioxide is deposited to fill the trench. To control a thickness of the deposited silicon dioxide, a chemical-mechanical-polishing process is performed to planarize the silicon dioxide and form a planar surface continuous with the upper surface of the hard mask layer. Finally, the hard mask layer is removed and the remaining silicon dioxide forms a uniform bit-line oxide layer.

US Patent:

62486357, Jun 19, 2001

Filed:

Oct 25, 1999

Appl. No.:

9/426205

Inventors:

David K. Foote - San Jose CA
Hideki Komori - Santa Clara CA
Bharath Rangarajan - Santa Clara CA
Steven K. Park - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438287

Abstract:

A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure to overlie the semiconductor substrate. Thereafter, a thin mask layer is formed to overlie the ONO structure to protect the ONO structure during a selective etch of a thick mask layer. The thick mask layer is formed to overlie the thin mask layer to protect the ONO structure during boron and arsenic implants. Thereafter, an etch process is performed in the ONO structure and a silicon oxide layer is formed to fill the etched area. A chemical-mechanical-polishing process is performed to planarize the silicon oxide layer and to form a planar surface continuous with an upper surface of the thick mask layer. The planarized silicon oxide layer functions as a bit-line oxide layer.