Hideaki Kawahara

US Patent:

20130193502, Aug 1, 2013

Filed:

Jan 17, 2013

Appl. No.:

13/744097

Inventors:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX, US
Hideaki KAWAHARA - Plano TX, US
Simon John MOLLOY - Allentown PA, US
Satoshi SUZUKI - Ushiku Ibaraki, JP
John Manning Savidge NEILSON - Norristown PA, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 29/78
H01L 29/66

US Classification:

257302, 257329, 438268

Abstract:

A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

US Patent:

20200373424, Nov 26, 2020

Filed:

Aug 11, 2020

Appl. No.:

16/990284

Inventors:

- Dallas TX, US
Simon John Molloy - Allentown PA, US
John Manning Savidge Neilson - Norristown PA, US
Hideaki Kawahara - Plano TX, US

International Classification:

H01L 29/78
H01L 29/66
H01L 29/06
H01L 29/08
H01L 29/423
H01L 29/10
H01L 29/40
H01L 29/417

Abstract:

A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

US Patent:

20190051721, Feb 14, 2019

Filed:

Oct 18, 2018

Appl. No.:

16/163606

Inventors:

- Dallas TX, US
Hideaki Kawahara - Plano TX, US
Sameer P. Pendharkar - Allen TX, US

International Classification:

H01L 49/02
H01L 21/02
H01L 21/306
H01L 29/06
H01L 21/762
H01L 21/3205
H01L 29/08
H01L 27/06
H01L 21/265

Abstract:

Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.

US Patent:

20180358258, Dec 13, 2018

Filed:

Jun 9, 2017

Appl. No.:

15/618642

Inventors:

- Dallas TX, US
ROBERT GRAHAM SHAW - NASHUA NH, US
HIDEAKI KAWAHARA - PLANO TX, US
ASAD MAHMOOD HAIDER - PLANO TX, US
YUJI MIZUGUCHI - FUKSHIMA, JP
HIROSHI YAMASAKI - FUKUSHIMA, JP
ABBAS ALI - PLANO TX, US
BRIAN GOODLIN - PLANO TX, US

International Classification:

H01L 21/74
H01L 27/12
H01L 29/06
H01L 29/78
H01L 29/10
H01L 21/84

Abstract:

A method of forming an integrated circuit includes forming ≥1 hard mask layer on a device layer on a BOX layer of a SOI substrate. A patterned masking layer is used for a trench etch to simultaneously form larger and smaller area trenches through the hard mask layer, device layer and the BOX layer. A dielectric liner is formed for lining the larger and smaller area trenches. A dielectric layer is deposited for completely filling the smaller area trenches and only partially filling the larger area trenches. The larger area trenches are bottom etched through the dielectric layer to provide a top side contact to the handle portion. The handle portion at a bottom of the larger area trenches is implanted to form a handle contact, and the larger area trenches are completely filled with an electrically conductive layer to form a top side ohmic contact to the handle contact.

US Patent:

20180076277, Mar 15, 2018

Filed:

Sep 13, 2016

Appl. No.:

15/264147

Inventors:

- Dallas TX, US
Hideaki Kawahara - Plano TX, US
Sameer P. Pendharkar - Allen TX, US

International Classification:

H01L 49/02
H01L 21/3205
H01L 21/762
H01L 21/02
H01L 21/265
H01L 29/08
H01L 21/306
H01L 29/06
H01L 27/06

Abstract:

A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.

US Patent:

20170062573, Mar 2, 2017

Filed:

Nov 9, 2016

Appl. No.:

15/347325

Inventors:

- Dallas TX, US
Simon John Molloy - Allentown PA, US
John Manning Savidge Neilson - Norristown PA, US
Hideaki Kawahara - Plano TX, US

International Classification:

H01L 29/40
H01L 29/10
H01L 29/417
H01L 29/78
H01L 29/06
H01L 29/08

Abstract:

A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

US Patent:

20170025525, Jan 26, 2017

Filed:

Oct 3, 2016

Appl. No.:

15/283523

Inventors:

- Dallas TX, US
Simon John Molloy - Allentown PA, US
John Manning Savidge Neilson - Norristown PA, US
Hideaki Kawahara - Plano TX, US

International Classification:

H01L 29/78
H01L 29/40
H01L 29/06
H01L 29/10
H01L 29/423
H01L 29/417
H01L 29/08

Abstract:

A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

US Patent:

20160240653, Aug 18, 2016

Filed:

Apr 27, 2016

Appl. No.:

15/139496

Inventors:

- Dallas TX, US
Hideaki Kawahara - Plano TX, US
Simon John Molloy - Allentown PA, US
Satoshi Suzuki - Ushiku Ibaraki, JP
John Manning Savidge Neilson - Norristown PA, US

International Classification:

H01L 29/78
H01L 21/311
H01L 29/417
H01L 29/08
H01L 29/10
H01L 29/40
H01L 29/06
H01L 29/66

Abstract:

A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.