Harry G Erhardt

US Patent:

46790900, Jul 7, 1987

Filed:

Jan 23, 1986

Appl. No.:

6/824556

Inventors:

Harry G. Erhardt - East Windsor NJ

Assignee:

RCA Corporation - Princeton NJ

International Classification:

H04N 314

US Classification:

35821326

Abstract:

Diagonally disposed line-selection artifacts appear in the video signal from a CCD imager using a line-transfer register, owing to differential delay in a side-loaded CCD shift register used for transferring charge packets from the image sensing array to the charge sensing output stage. The extent of these line-selection artifacts is shortened in the direction of line scan by spatial multiplexing, so they occur entirely within line retrace intervals. The line-selection artifacts are then suppressed by normal line retrace blanking.

US Patent:

46865748, Aug 11, 1987

Filed:

Apr 4, 1986

Appl. No.:

6/848223

Inventors:

Harry G. Erhardt - East Windsor NJ

Assignee:

RCA Corporation - Princeton NJ

International Classification:

H04N 314

US Classification:

35821326

Abstract:

A CCD imager has a line-transfer register the contents of which are transferred at pixel scan rate, one or two lines at a time, through a side-loaded CCD shift register forward clocked at a multiple of pixel scan rate, to an electrometer. Forward clocking the CCD shift register at higher rate than pixel scan rate reduces the differential delay between the various points of side-loading the CCD shift register, so line selection artifacts are confined to the line retrace interval. Line selection artifacts are then suppressed by normal line-retrace-interval blanking.

US Patent:

50362194, Jul 30, 1991

Filed:

May 31, 1989

Appl. No.:

7/359176

Inventors:

Andrew G. F. Dingwall - Princeton NJ
Victor Zazzu - Belle Mead NJ
Harry G. Erhardt - Lawrenceville NJ

Assignee:

Harris Corporation - Melbourne FL

International Classification:

G11C 2702

US Classification:

307353

Abstract:

A precise, high speed CMOS track (sample)/hold circuit uses a first circuit leg including four Schottky barrier diodes configured to form a Wheatstone bridge, a second leg with a single n-channel MOS transistor, an essentially constant current source having MOS transistors, a capacitor for holding output signal, and reverse biasing circuitry having MOS transistors for selectively reverse biasing the four diodes. An analog input signal is applied to the cathode of the first diode and to the anode of the second diode. An output signal of the same magnitude and polarity as the input signal is generated at an output terminal (the cathode of the third diode and the anode of the fourth diode) of the circuit when current flows through the first circuit leg. When the current flowing through the first circuit leg is switched to the second circuit leg, the capacitor, which is connected to an output terminal of the circuitry, holds the generated output signal level and the reverse biasing circuitry reverse biases all of the diodes so as to isolate the capacitor from all other components of the circuit.