An absolute value circuit includes an operational amplifier, the output of which is coupled to control inputs of complementary polarity transistors having current flow paths therethrough coupled in series with inputs of current mirror amplifier stages. A common node of the current flow paths through the transistors is coupled to an input of the operational amplifier to which a current waveform is applied. The current mirror amplifier stages are configured so as to provide like polarity output currents. The outputs of the current mirror amplifier stages are combined to produce an output current that corresponds to a full wave rectification or absolute value of an input current coupled to the operational amplifier.
Margining Pin Interface Circuit For Clock Adjustment Of Digital To Analog Converter
A voltage margin setting interface circuit has a single input pin, and is configured to program the slew rate and polarity direction of variation of the operation of a digital-to-analog converter, such as may be used to set a reference voltage level, for application to an error amplifier of a voltage regulator circuit of the power supply of a personal computer. A DAC clocking control circuit is coupled to an output port, and to respective DAC increment and decrement ports, and is operative to control the magnitude of output current, and to assert an output signal at one of the increment and decrement ports, in accordance with a prescribed relationship between the voltage and upper and lower ranges of the input voltage relative to its middle value.
A voltage margin circuit has an input that receives a control voltage for programming an output reference voltage. The control voltage is coupled through an input resistor to an operational amplifier, referenced to a voltage midway between the voltage range of the input voltage and having its output coupled to a pair of transistors, whose current flow paths are coupled to inputs of a first pair of current mirrors. Outputs of the first current mirrors pair are cross-coupled to inputs of a second current mirrors pair. Outputs of the second current mirror pair are coupled through an output resistor to a prescribed voltage. The output reference voltage is the sum of the prescribed voltage and an offset as the product of the output resistor and an output current supplied by one of the third and fourth current mirrors.
Protective Network For An Insulated-Gate Field-Effect (Igfet) Differential Amplifier
Harold Allen Wittlinger - Pennington NJ Michael Scott Fisher - Farmers Branch TX
Assignee:
RCA Corporation - New York NY
International Classification:
H03F 345 H02H 320
US Classification:
330207P
Abstract:
The input stage of an amplifier includes two input terminals to which are connected the gates of two, differentially connected, IGFETs protected by two diodes connected back-to-back (in series) between the gates. The amplifier also includes means for applying an external signal source to one input terminal, means for shorting the diode connected to the other input terminal, and means for negatively feeding back the output of the amplifier to its input. This maintains the potential difference across the diode connected to the input terminal to which the external signal source is connected close to zero volt thereby substantially eliminating any leakage current through it.
Electrical System With Small Signal Suppression Circuitry
Salomon Vulih - Neshanic St. NJ Stephen J. Glica - Somerset NJ Harold Allen Wittlinger - Pennington NJ
Assignee:
Harris Corporation - Melbourne FL
International Classification:
F02P 515
US Classification:
327 91
Abstract:
In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.
A circuit is disclosed for detecting ground faults and neutral faults and for providing power interruption in response thereto. The circuit monitors the current flow in the line and neutral conductors and provides a signal to a power interruption circuit in the event that a ground fault or a neutral fault condition is detected. In addition, a signal having a certain frequency is generated and coupled on the neutral line to enhance the probability of detecting neutral faults.
Raymond L. Giordano - Flemington NJ Harold A. Wittlinger - Pennington NJ
Assignee:
Harris Corp. - Melbourne FL
International Classification:
H03K 522
US Classification:
327 63
Abstract:
A transconductance amplifier suitable for the input stage of a comparator with the capability of amplifying input signal with common mode voltage components in a range including the entirety of its operating voltage. Operation at one voltage extreme is accomplished by use of a long tailed pair connection of a pair of bulk modulated FETs with gates at the input terminals of the amplifier. Operation at the other voltage extreme is accomplished by the use of a pair of FETs in a source follower mode to drive common gate transistors of opposite polarity, the gates of the FETs also being connected to the input terminals of the amplifier. A common high impedance load for the comparator is connected to current mirrors of the drains of both pairs of FETs in the amplifier. The circuit may be implemented with bipolar transistors and additional amplification provided. Methods of comparing voltages are also disclosed.
A bandgap reference voltage generating circuit develops a predetermined reference potential between first and second terminals. A pair of transistors are operated at different emitter current densities to develop a difference between their base-emitter potentials. That difference is applied across a first resistance and is increased and applied across a second resistance. The reference potential comprises the sum of at least the scaled-up potential and the conduction potential of a semiconductor junction. A regulating transistor completes a degenerative feedback connection and controls the current flowing between the first and second terminals responsive to the reference potential departing from the predetermined value. A regenerative feedback connection responds to the current in the regulating transistor to decrease the potential across the second resistance when the controlled current increases.
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