Hans J Chandra

US Patent:

20090097343, Apr 16, 2009

Filed:

Oct 16, 2007

Appl. No.:

11/873290

Inventors:

KERFEGAR K. KATRAK - FENTON MI, US
HANS CHANDRA - CARMEL IN, US
TIMOTHY A. WELLSAND - PERU IN, US

Assignee:

GM GLOBAL TECHNOLOGY OPERATIONS, INC. - DETROIT MI

International Classification:

G11C 29/02

US Classification:

365201

Abstract:

Method and systems are described for testing an address line inter- coupling a processor and a memory. The contents of a first address in the memory are initially compared with the contents of a second address in the memory, wherein each of the first and second addresses are addressable in the memory by a different value applied on the address line. If the contents of the first and second addresses match, the contents of either one of the first and second addresses are changed, and a subsequent comparison of the contents of the first and second memory addresses is performed. If the second comparison determines that contents of the first and second memory address still match, then a fault condition associated with the address line is identified.