Hailong Yao

US Patent:

20110078638, Mar 31, 2011

Filed:

Sep 28, 2010

Appl. No.:

12/892371

Inventors:

Andrew B. Kahng - Del Mar CA, US
Hailong Yao - La Jolla CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

G06F 17/50

US Classification:

716 52

Abstract:

The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.

US Patent:

20130159945, Jun 20, 2013

Filed:

Feb 13, 2013

Appl. No.:

13/766349

Inventors:

The Regents of the University of California - Oakland CA, US
Hailong Yao - La Jolla CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

G06F 17/50

US Classification:

716 52

Abstract:

The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.