Haihua S Su

US Patent:

6898769, May 24, 2005

Filed:

Oct 10, 2002

Appl. No.:

10/268236

Inventors:

Sani Richard Nassif - Austin TX, US
Haihua Su - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

716 5, 716 2, 716 8, 716 9, 716 10, 716 11

Abstract:

A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a first layout of the integrated circuit with empty spaces between the adjacent cells, and the placement of the cells is changed to a second layout wherein the size of the empty spaces between the adjacent cells also change. The decoupling capacitors are placed in the empty spaces of the second layout. In the example of a row-oriented cell structure, the empty spaces may be uniformly distributed along each row for the initial layout. An adjoint sensitivity analysis is performed of the sensitivity of a noise function of the integrated circuit with respect to sizes of the empty spaces between adjacent cells, and an original noise waveform is convolved with an adjoint noise waveform. The convolution may use piecewise linear compressions of the original and adjoint noise waveforms. A quadratic programming solver is then used to iteratively determine the sizes of the empty spaces between adjacent cells.

US Patent:

7346867, Mar 18, 2008

Filed:

Feb 1, 2005

Appl. No.:

11/048422

Inventors:

Haihua Su - Austin TX, US
David J. Widiger - Pflugerville TX, US
Ying Liu - Austin TX, US
Byron L. Krauter - Round Rock TX, US
Chandramouli V. Kashyap - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6

Abstract:

A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

US Patent:

7761275, Jul 20, 2010

Filed:

Dec 19, 2005

Appl. No.:

11/311038

Inventors:

Kaviraj S. Chopra - Ann Arbor MI, US
Chandramouli V. Kashyap - Round Rock TX, US
Haihua Su - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06G 7/62

US Classification:

703 14, 703 13, 703 15, 716 4, 716 5, 716 6

Abstract:

A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.

US Patent:

6842714, Jan 11, 2005

Filed:

Aug 22, 2003

Appl. No.:

10/646426

Inventors:

Emrah Acar - Austin TX, US
Anirudh Devgan - Austin TX, US
Ying Liu - Austin TX, US
Sani R. Nassif - Austin TX, US
Haihua Su - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 2100
G06F 1900
G06F 1500

US Classification:

702136, 702 60, 702 64

Abstract:

A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.