Hai P Longworth

US Patent:

7302757, Dec 4, 2007

Filed:

Aug 16, 2005

Appl. No.:

11/204699

Inventors:

Jeffrey A. Brody - Hopewell Junction NY, US
Hsichang Liu - Fishkill NY, US
Hai Pham Longworth - Poughkeepsie NY, US
James C. Monaco - Stormville NY, US
Gerard J. Nuzback - Hopewell Junction NY, US
Wei Zou - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01K 3/10

US Classification:

29852, 29825, 29846

Abstract:

An improved Land Grid Array interconnect structure is provided with the use of small metal bumps on the substrate electrical contact pad. The bumps interlock with segments of the fuzz button connection and increase the physical contact surface area between the contact pad and fuss button. The improved contact reduces displacement of electrical contact points due to thermo-mechanical stress and lowers the required actuation force during assembly.

US Patent:

8232655, Jul 31, 2012

Filed:

Jan 3, 2008

Appl. No.:

11/968663

Inventors:

Charles L. Arvin - Poughkeepsie NY, US
Hai P. Longworth - Poughkeepsie NY, US
David J. Russell - Apalachin NY, US
Krystyna W. Semkow - Poughquag NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/495
H01L 21/44

US Classification:

257781, 257676, 257750, 257766

Abstract:

An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

US Patent:

8367543, Feb 5, 2013

Filed:

Mar 21, 2006

Appl. No.:

11/308396

Inventors:

Mukta Ghate Farooq - Hopewell Junction NY, US
Jasvir Singh Jaspal - Poughkeepsie NY, US
William Francis Landers - Wappingers Falls NY, US
Thomas E. Lombardi - Poughkeepsie NY, US
Hai Pham Longworth - Poughkeepsie NY, US
H. Bernhard Pogge - Hopewell Junction NY, US
Roger A. Quon - Rhinebeck NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44
H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

438653, 438613, 438614, 257738, 257751

Abstract:

A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

US Patent:

8587112, Nov 19, 2013

Filed:

Apr 23, 2012

Appl. No.:

13/453074

Inventors:

Charles L. Arvin - Poughkeepsie NY, US
Hai P. Longworth - Poughkeepsie NY, US
David J. Russell - Apalachin NY, US
Krystyna W. Semkow - Poughquag NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 3/00

US Classification:

257690, 29829, 257750, 257766, 257E23037

Abstract:

An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

US Patent:

20050221635, Oct 6, 2005

Filed:

Mar 30, 2004

Appl. No.:

10/708887

Inventors:

Jeffrey Brody - Hopewell Junction NY, US
Hsichang Liu - Fishkill NY, US
Hai Longworth - Poughkeepsie NY, US
James Monaco - Stormville NY, US
Gerard Nuzback - Hopewell Junction NY, US
Wei Zou - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01R012/00

US Classification:

439071000

Abstract:

An improved Land Grid Array interconnect structure is provided with the use of small metal bumps on the substrate electrical contact pad. The bumps interlock with segments of the fuzz button connection and increase the physical contact surface area between the contact pad and fuzz button. The improved contact reduces displacement of electrical contact points due to thermo-mechanical stress and lowers the required actuation force during assembly.

US Patent:

20060211167, Sep 21, 2006

Filed:

Mar 18, 2005

Appl. No.:

10/907062

Inventors:

John Knickerbocker - Wappingers Falls NY, US
Hai Longworth - Poughkeepsie NY, US
Roger Quon - Rhinebeck NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/00
H01L 23/02

US Classification:

438106000, 257678000

Abstract:

Disclosed are microelectronic structures based on improved design and material combinations to provide improved current capabilities per I/O. The preferred embodiment of the invention uses a combination of one or more of the following: (1) Underbump metallurgy which enhances current per I/O by increasing via diameter or by having multiple via openings under BLM; (2) Thicker underbump metallurgy, where use of good conductor metallurgies can be used with increased thickness; (3) Utilizing larger via diameter under bump metallurgy, larger solder bump diameter and/or other current enhancing features for power and/or ground via connections; and (4) Using additives in Pb-free alloys to alter microstructure to minimize migration of atoms in the solder or at intermetallic transitions.

US Patent:

6391669, May 21, 2002

Filed:

Jun 21, 2000

Appl. No.:

09/598426

Inventors:

Benjamin V. Fasano - New Windsor NY
Hai P. Longworth - Poughkeepsie NY
Anthony L. Plachy - Crompond NY
Robert N. Wiggin - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3104

US Classification:

438 18, 29593

Abstract:

Multilayer substrates, are fabricated with the incorporation therein of non-destructive test structures utilized to provide visual and electrical test data to facilitate the ascertainment and assessment of potential electrical interface failures. Furthermore, there are provided embedded structures in multilayer substrates, such as are employed in chip carrier packaging, so as to facilitate electrical testing for via to via alignment and interface layer alignment, and to enable the testing of conductive interface electrical integrity of multilayer electrical devices.