Grant J Mcneil from 285 Brennan Woods Dr, Saint George, VT 05495, age 56, Phone: 802 879-4969

Resumes

Design Engineer

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Location:

1735 Technology Dr, San Jose, CA 95110

Industry:

Semiconductors

Work:

Nanya Technology since Jul 2008
Design Engineer
Qimonda Nov 2000 - Jul 2008
Senior Staff Engineer Design Analysis & Characterization
Siemens / Infineon Nov 1998 - Nov 2000
Lead Development Characterization Eng
Siemens Jun 1996 - Nov 1998
Technical Failure Analysis Manager
Motorola UK Ltd 1990 - 1996
Failure Analysis / Product Engineer

Education:

University of Paisley 1985 - 1990

Skills:

Cmos
Semiconductors
Dram
Failure Analysis
Ic
Characterization
Vlsi
Testing
Verilog
Physical Design
Mixed Signal
Product Engineering
Dynamic Random Access Memory
Asic
Analog
Soc
Cadence Virtuoso

Us Patents

Test Mode For Ipp Current Measurement For Wordline Defect Detection
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US Patent:

7257038, Aug 14, 2007
Filed:

Jan 3, 2006
Appl. No.:

11/322252
Inventors:

Michael A. Killian - Richmond VT, US
Martin Versen - Burlington VT, US
Grant McNeil - Williston VT, US
Zach Johnson - Williston VT, US
Changduk Kim - South Burlington VT, US
Assignee:

Infineon Technologies AG - Neubiberg
International Classification:

G11C 7/00
US Classification:

365201, 36518509, 36523006
Abstract:

A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

Electro-Static Discharge Protection Circuit And Method For Making The Same
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US Patent:

20040256675, Dec 23, 2004
Filed:

Jun 17, 2003
Appl. No.:

10/464382
Inventors:

Grant McNeil - Williston VT, US
Assignee:

Infineon Technologies North America Corp. - San Jose CA
International Classification:

H01L023/62
US Classification:

257/355000, 257/329000
Abstract:

As disclosed herein, an electrostatic discharge (ESD) protection circuit is provided for an integrated circuit including a semiconductor substrate. The ESD protection circuit includes a plurality of active devices formed in the semiconductor substrate, the active devices being formed by a process including a plurality of steps carried out to form, at the same time, a plurality of active devices having a function other than ESD protection. For example, the ESD circuit may include an array of vertical transistors formed according to a process including many of the steps used to form, at the same time, vertical transistors of a DRAM array. Also disclosed is the formation of an ESD circuit in an “unusable” area of a semiconductor chip, such as under a bond pad, land or under bump metallization of the chip.

Integrated Circuit Including Decoupling Capacitors That Can Be Disabled
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US Patent:

20090040857, Feb 12, 2009
Filed:

Aug 8, 2007
Appl. No.:

11/835675
Inventors:

Grant McNeil - Williston VT, US
Ernst Stahl - Essex Junction VT, US
International Classification:

G11C 5/14
US Classification:

365226
Abstract:

An integrated circuit includes a decoupling capacitor configured to be enabled in response to the decoupling capacitor not increasing a standby current of the integrated circuit and disabled in response to the decoupling capacitor increasing the standby current of the integrated circuit.