Graham G Yarbrough

US Patent:

20020004835, Jan 10, 2002

Filed:

Jun 1, 2001

Appl. No.:

09/872756

Inventors:

Graham Yarbrough - Sandy Hook CT, US

Assignee:

INRANGE Technologies Corporation - Lumberton NJ

International Classification:

G06F015/16

US Classification:

709/230000, 709/206000

Abstract:

A message queue server emulates a computer peripheral that not only supports communication between two mainframes, but also provides a gateway to open systems computers, networks, and other similar message queue servers. The message queue server provides protocol-to-protocol conversion from mainframes to today's computing systems in a manner that does not require businesses that own the mainframes to rewrite legacy applications to share data with other mainframes and open systems. The message queue server emulates a mainframe peripheral coupled to a first mainframe having a first protocol. The system includes digital storage to temporarily store information from the first mainframe. The system includes at least one manager that (i) coordinates the transfer of the information of the first protocol between the mainframe peripheral emulator and the digital storage and (ii) coordinates transfer of the information between the digital storage and (a) a second mainframe having a second protocol or (b) a computer network having a third protocol. Preferably, the message queue server emulates a tape drive and arranges the stored messages in a queue. Optionally, the message queue server manages the message queues as a function of information usually found in a standard tape label.

US Patent:

20020083200, Jun 27, 2002

Filed:

Dec 21, 2001

Appl. No.:

10/024564

Inventors:

Jens Haulund - Trumbull CT, US
Donald Denton - North Haven CT, US
Graham Yarbrough - Sandy Hook CT, US

Assignee:

Inrange Technologies Corporation

International Classification:

G06F015/16

US Classification:

709/245000, 709/203000

Abstract:

An apparatus and method for dynamic resource mapping in a TCP/IP environment that includes a DRM server component, a client side DRM process for collecting machine specific performance characteristics, a client/server protocol to allow communication of machine specific process characteristics between the DRM server component and the client side DRM process and a DRM protocol to allow a client to request an application resource by name and the DRM server to return a selected address of a client, the selection made based upon collected machine specific performance characteristics of at least one client. Furthermore, the invention updates the DRM server to reflect the operability of the application and as a result does not return the address of the resource if it is inoperable.

US Patent:

20030110265, Jun 12, 2003

Filed:

Dec 7, 2001

Appl. No.:

10/004878

Inventors:

Mark Lutian - Clinton CT, US
Graham Yarbrough - Sandy Hook CT, US

Assignee:

Inrange Technologies Inc.

International Classification:

G06F015/16

US Classification:

709/227000, 711/111000, 703/021000, 709/246000

Abstract:

An apparatus and method for providing simultaneous access to data on a mainframe computer. The apparatus includes an emulation, which contains the data, appears to a mainframe computing system as a peripheral device. The peripheral provides access to the data to a plurality of requesters simultaneously through the creation of unique nominal IDs for each request.

US Patent:

20020002631, Jan 3, 2002

Filed:

Jun 1, 2001

Appl. No.:

09/872778

Inventors:

Jens Haulund - Trumbull CT, US
Graham Yarbrough - Sandy Hook CT, US

Assignee:

INRANGE Technologies Corporation - Lumberton NJ

International Classification:

G06F009/46

US Classification:

709/314000

Abstract:

The system comprises a first processor, a second processor and non-volatile memory. The non-volatile memory stores messages being transferred between the first and second processors. The non-volatile memory is resettably and logically decoupled from first and second processors to preserve the state of the first and second processors and the messages in the event of a loss of communication or a processor reset. The non-volatile memory increases the rate of message transfer by transferring blocks of messages between the non-volatile memory and the second processor. The non-volatile memory includes status and control registers to store the state of messages being transferred, message queues, and first and second processors. The system may also include a local power source to provide power to the non-volatile memory.