Glenn Edward Starnes

US Patent:

7397722, Jul 8, 2008

Filed:

Feb 2, 2007

Appl. No.:

11/670632

Inventors:

Glenn E. Starnes - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 7/00

US Classification:

36523003, 36518905, 365190, 365203

Abstract:

A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.

US Patent:

7518947, Apr 14, 2009

Filed:

Sep 28, 2006

Appl. No.:

11/536136

Inventors:

Glenn E. Starnes - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 8/18

US Classification:

36523311, 365194, 365193, 3652335

Abstract:

A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.

US Patent:

7746716, Jun 29, 2010

Filed:

Feb 22, 2007

Appl. No.:

11/677808

Inventors:

Mark W. Jetton - Austin TX, US
Lawrence F. Childs - Austin TX, US
Olga R. Lu - Austin TX, US
Glenn E. Starnes - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 7/00
G11C 7/02
G11C 8/00

US Classification:

3652101, 36521015, 3652303, 3652331, 365205, 365207, 365208

Abstract:

A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.

US Patent:

55549420, Sep 10, 1996

Filed:

Mar 13, 1995

Appl. No.:

8/402787

Inventors:

Lawrence N. Herr - Coupland TX
Glenn E. Starnes - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03K 19003

US Classification:

326 33

Abstract:

An integrated circuit memory (114) has a power supply independent address buffer (50) that comprises an inverter (60), a bipolar transistor (67), and a P-channel transistor (68). The inverter (60) has an output terminal coupled to a base of the bipolar transistor (67). The P-channel transistor (63) is for injecting a current at the output terminal of the inverter in response to a reference voltage. The reference voltage varies proportionally to variations of a power supply voltage in order to compensate for gate-to-source voltage changes of a P-channel transistor (61) of the inverter (60) that occurs as a result of a changing power supply voltage. For address buffer (50), a range of address transition times as a function of power supply voltage is decreased, thus improving an address set-up and hold time of the integrated circuit memory (114).

US Patent:

6108266, Aug 22, 2000

Filed:

Oct 28, 1999

Appl. No.:

9/428440

Inventors:

William Robert Weier - Austin TX
Ray Chang - Austin TX
Glenn Starnes - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 800

US Classification:

36523008

Abstract:

A memory utilizing programmable delay circuits to control address buffers. A programmable delay device is provided for each block of a plurality of blocks of the memory device. Each block is associated with a corresponding bit array for storing data for the associated block. The delay device is used to delay activation of sense amplifiers from the time the block is selected which, in turn, corresponds to the duration of the addresses that are provided to the bit array within the block. Each of the delays within each block is programmed by a global fuse circuit, so that all of the blocks are programmed with the same delay. After fabrication of the memory device onto an integrated circuit (IC), all of the data paths within each block are measured under various voltage and temperature conditions to identify the slowest data path of all blocks of the memory device. Once a particular delay is identified for the slowest data path within the memory device, all of the programmable delays within each block are programmed with a corresponding delay. In this manner, all of the sense amplifiers within any selected blocks are activated after the programmed delay to ensure valid data.

US Patent:

61575836, Dec 5, 2000

Filed:

Mar 2, 1999

Appl. No.:

9/261876

Inventors:

Glenn E. Starnes - Austin TX
Stephen T. Flannagan - Austin TX
Ray Chang - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 700

US Classification:

365200

Abstract:

Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.

US Patent:

20210294374, Sep 23, 2021

Filed:

Jun 3, 2021

Appl. No.:

17/338550

Inventors:

- Santa Clara CA, US
Daniel CUMMINGS - Austin TX, US
Glenn STARNES - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/06
G11C 7/10
G06F 1/3206

Abstract:

Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

US Patent:

20200333825, Oct 22, 2020

Filed:

Apr 16, 2019

Appl. No.:

16/386070

Inventors:

- Santa Clara CA, US
Daniel CUMMINGS - Austin TX, US
Glenn STARNES - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/06
G06F 1/3206
G11C 7/10

Abstract:

Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.