An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.
A high frequency CMOS voltage level shifter providing either an inverted or noninverted signal output shifted in voltage level from an input signal. The level shifter includes two pairs of metal oxide semiconductor transistors with the transistors of each pair connected together and respectively connected to a first and second voltage source. The gates of a transistor in each pair are cross connected to the interconnected drains of the opposing transistor pair. First and second conducting elements are respectively connected to the cross connected transistor gates to discharge a transient capacitive gate charge present during output signal voltage level shifting.
A power supply switching circuit is disclosed which provides for automatically switching an electrical circuit load from a main power source to an auxiliary power source, yet maintains the two power sources isolated from each other. The power supply switching circuit is readily integrated with its electrical load to form a monolithic integrated circuit. A pair of MOSFETs provides alternate connections of the load to the respective power sources. The circuit effectively connects the gate and source of the appropriate MOSFET across the available power source and thus assures the maximum turn-on voltage is applied to the MOSFET.
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