Glen O Sescila from 3003 Drake Cv, Leander, TX 78645, Phone: 512 267-3883

Us Patents

System And Method For Connecting Peripheral Buses Through A Serial Bus
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US Patent:

6425033, Jul 23, 2002
Filed:

Jun 5, 1998
Appl. No.:

09/092342
Inventors:

Craig M. Conway - Round Rock TX
Kevin Schultz - Georgetown TX
B. Keith Odom - Georgetown TX
Glen Sescila - Pflugerville TX
Bob Mitchell - Austin TX
Ross Sabolcik - Austin TX
Robert Hormuth - Cedar Park TX
Assignee:

National Instruments Corporation - Austin TX
International Classification:

G06F 1338
US Classification:

710128, 710129, 710107, 710 62, 710 63
Abstract:

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus.

System And Method For Handling Device Retry Requests On A Communication Medium
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US Patent:

6640312, Oct 28, 2003
Filed:

Aug 1, 2000
Appl. No.:

09/629349
Inventors:

Andrew Thomson - Austin TX
David W. Madden - Austin TX
Glen Sescila - Pflugerville TX
Aljosa Vrancic - Austin TX
Assignee:

National Instruments Corporation - Austin TX
International Classification:

G06F 1100
US Classification:

714 5, 714 9, 714 43
Abstract:

A system and method for transferring data over a communications medium. A host is coupled to a device through a serial bus lacking error handling capabilities, such as an IEEE 1394 bus. The host may control the device by sending requests accessing its memory registers. The host generates a first request to the device to access a memory address location of the device, and which includes an address and status information indicating whether a prior request to the memory address location returned successfully. The device examines the status information to determine if it is a retry of a prior request, and if so, determines if the prior request completed successfully to the memory address location by comparing the address and data transfer size of the first request to those of the prior request. If identical, then the prior request completed successfully to the memory address location, and the request is ignored. Otherwise, the device retries the prior request.

System And Method For Coupling Peripheral Buses Through A Serial Bus Using A Split Bridge Implementation
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US Patent:

20010037423, Nov 1, 2001
Filed:

Jun 6, 2001
Appl. No.:

09/876003
Inventors:

Craig Conway - Round Rock TX, US
Kevin Schultz - Georgetown TX, US
B. Odom - Georgetown TX, US
Glen Sescila - Pflugerville TX, US
Bob Mitchell - Austin TX, US
Ross Sabolcik - Austin TX, US
Robert Hormuth - Cedar Park TX, US
Assignee:

National Instruments Corporation
International Classification:

G06F013/00
G06F013/38
US Classification:

710/129000
Abstract:

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge. Each of the primary bridge and secondary bridge include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively. The primary bridge and the secondary bridge collectively implement a PCI-PCI bridge register set.

Digital Delay Elements Constructed In A Programmable Logic Device
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US Patent:

20050046458, Mar 3, 2005
Filed:

Aug 28, 2003
Appl. No.:

10/651124
Inventors:

Charles Schroeder - Round Rock TX, US
Daniel Baker - Austin TX, US
Glen Sescila - Pflugerville TX, US
International Classification:

H03H011/26
US Classification:

327276000
Abstract:

A delay circuit. In one embodiment, a programmable logic device (PLD) is used to implement one or more delay circuits having a plurality of delay elements. Included in the plurality of elements are a balanced number of logic elements such that rising and falling edges of a signal passing through the delay circuit propagate with substantially the same amount of delay. The delay circuit may also include a selector circuit coupled to select an output from one of the plurality of delay elements. The delay circuit may be implemented such that it preserves the duty cycle and/or pulse width of signals to which the delay is applied.

Method And Apparatus For Optimizing The Responsiveness And Throughput Of A System Performing Packetized Data Transfers Using A Transfer Count Mark
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US Patent:

20070022204, Jan 25, 2007
Filed:

Jul 21, 2005
Appl. No.:

11/186183
Inventors:

Andrew Moch - Austin TX, US
Aaron Rossetto - Austin TX, US
Brent Schwan - Austin TX, US
Glen Sescila - Austin TX, US
International Classification:

G06F 15/16
US Classification:

709230000
Abstract:

A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

Pci Bus To Ieee 1394 Bus Translator Employing Write Pipe-Lining And Sequential Write Combining
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US Patent:

58753133, Feb 23, 1999
Filed:

Apr 8, 1997
Appl. No.:

8/826920
Inventors:

Glen O. Sescila - Pflugerville TX
Brian K. Odom - Pflugerville TX
Kevin L. Schultz - Pflugerville TX
Assignee:

National Instruments Corporation - Austin TX
International Classification:

G06F 1300
US Classification:

395309
Abstract:

A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer.

Pci Bus To Ieee 1394 Bus Translator Employing Pipe-Lined Read Prefetching
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US Patent:

59371757, Aug 10, 1999
Filed:

Apr 8, 1997
Appl. No.:

8/826925
Inventors:

Glen O. Sescila - Pflugerville TX
Brian K. Odom - Pflugerville TX
Kevin L. Schultz - Pflugerville TX
Assignee:

National Instruments Corporation - Austin TX
International Classification:

G06F 1338
US Classification:

395309
Abstract:

A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer.

Pci Bus To Ieee 1394 Bus Translator
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US Patent:

59535113, Sep 14, 1999
Filed:

Apr 8, 1997
Appl. No.:

8/835527
Inventors:

Glen O. Sescila - Pflugerville TX
Brian K. Odom - Pflugerville TX
Kevin L. Schultz - Pflugerville TX
Assignee:

National Instruments Corporation - Austin TX
International Classification:

G06F 1338
G06F 1300
G06F 1340
US Classification:

395309
Abstract:

A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer.